Simulating a circuit design before committing it to silicon is always the wise thing to do, since problems can be caught before they become costly mistakes. Analog designers’ familiarity with Spice1 often leads them to ask for Spice models of analog-to-digital converters (ADCs).

When designers ask me for such models, I ask what they need from an ADC model. Most designers want models that show how the converter’s input interacts with the external circuitry driving the ADC. One example of this is simulating the buffer amplifier’s stability when charging the internal sampling capacitor of a successive-approximation register (SAR) ADC.

Other engineers want to simulate loading on the voltage-reference input (for similar buffer optimization). They might want a transfer function that shows the noise and frequency response of the system, from system input to ADC input, perhaps with an “effective analog output” that takes these effects into account. It’s perhaps not surprising that no one seems much concerned about simulating the ADC’s digital behavior in Spice!

Some manufacturers offer Spice models for their ADC front ends. For example, Texas Instruments2 has several for high-speed pipeline converters and precision SAR converters. In most cases, though, you’ll have to create your own.

### Modeling SAR Operation

An SAR ADC compares an analog input signal to a reference voltage and produces a digital representation of that comparison. Conversion accuracy depends primarily on how accurately the signal is captured. If the signal has perfectly settled, the results of the conversion will accurately represent that signal (minus the inherent error of the ADC). If the input drive circuitry does not permit the analog input signal to settle to the correct value, the conversion will be incorrect.

Figure 1 is a simplified model of a SAR ADC input stage. The equivalent input elements include an internal input RC pair (RS1, CSH), two switches (S1, S2), and VSH0, the initial voltage across the sampling capacitor, CSH. This voltage can be ground, the previous conversion, or the reference voltage (depending on the converter’s input structure).

1. The sample-and-hold function of modern SAR converters can be represented by this equivalent circuit. RS1 is the on resistance of the sampling switch (S1), while S2 and VSH0 reset the voltage on the sampling capacitor before a new sample is taken.

The signal is acquired by opening S2 and closing S1. When S1 closes, CSH charges (or discharges) through RS1, so VCSH rises or falls to (eventually) equal VIN.

To make sure the value of the input signal is accurately transferred to CSH, an op amp is commonly used to drive the input, through an RC circuit. Selecting the appropriate op amp and RC values has been extensively documented.3, 4, 5, 6 A poor choice of amplifier and/or component values keeps the input signal from settling properly. CSH is charged to the wrong voltage and the ADC converts the incorrect value.

Figure 2 shows the charge spikes on the ADC’s input pin during sampling. The top curve (trace 4) shows the trigger signal that tells the converter to sample the input signal, then initiate the conversion.

2. With high source impedances, the current required to charge the sampling capacitor causes large spikes on the ADC input pin. These spikes must settle within the converter’s acquisition time, or the conversion will be incorrect.

This trigger closes and opens the converter’s analog input switch. On the falling edge of the trigger signal, the input switch closes, connecting the internal sampling capacitor CSH to the input analog signal. On the rising edge of the trigger signal, the input analog switch opens, disconnecting the sampling capacitor from the input signal. The actual conversion from analog to digital begins at that instant.

During the sampling process, the ADC’s analog input pin (trace 1) demands varying amounts of charge, depending on the amplitude of the input signal and the results of the previous conversion. In Figure 2, the charging waveform is captured with an oscilloscope’s low-capacitance probe that senses the voltage drop across a 10k resistor between the signal and the ADC’s input pin. (The 10k resistor is present only to provide a voltage proportional to the charge flowing. It’s not a good idea to drive the front end of a SAR ADC through a high source impedance!)

Figure 3 shows the input loading in greater detail. The top curve (trace R1) is the ADC’s chip select (CS#), which also acts as the start-of-acquisition signal. The middle curve (trace R2) is the serial clock (SCLK), provided by the external control logic. The bottom trace (ADC_IN) shows the signal captured at the ADC’s input.

3. An incorrectly designed drive circuit doesn’t allow the input to settle to the required accuracy within the acquisition time. The converter sees only the voltage present at the time the acquisition cycle ends.

For this example, an RC network with an excessively long time constant is placed in front of the ADC’s input pin. This keeps the capacitor’s voltage from reaching the actual signal value during the sampling period. The ADC data output therefore does not correctly represent the input analog signal.

Making sure the drive op amp and RC network are optimum is a good use of Spice. Let’s see how you can construct a model to verify your design. (The following model and test bench were developed using TI’s free Spice simulator, TINA-TI7.)

Correct conversion requires the voltage on the sampling capacitor at the end of the acquisition period to be within the voltage equivalent to 0.5 least-significant bit (LSB) of the actual value. A model of the front end should be able to show the voltage on the sampling capacitor at this time and compare it with the input voltage. The difference should be less than one-half LSB of the full-scale range. For the 16-bit ADS8326, half an LSB would be 39 µV. The ADS8326 LSB is found by:

LSB = 2 VREF/216

where VREF = 2.5 V, making the full-scale range 5 V.

Figure 4 is a test bench for an ADC input model. On the left is a sample-and-hold circuit using ideal switches. The ideally sampled input voltage is “displayed” on VM1. On the right is a simple model of the ADS8326 sample-and-hold circuit, built using information from the datasheet. The sampling process is controlled by the Sample voltage source, which is a piece-wise linear (PWL) source in Spice. The timing is taken from the ADC datasheet.

4. This is a test bench for a SAR ADC input model. The ideal input is on the left. A model of the real-world ADC is on the right. It closely mimics the circuit of Figure 2. VCVS2 and SW6 provide consistency with the ideal sample-and hold-circuit on the left. Combining both models in a single simulation makes it easy to compare the output waveforms.

The sampling switch has an RON of 50 Ω, and the input capacitor is 48 pF (assuming single-ended configuration). What isn’t apparent from the datasheet is that the voltage across the sampling capacitor is reset to a midpoint value (with respect to the ADC full-scale range) when conversion is complete. The circuit driven by VReset performs this function. VSH measures the held voltage across the capacitor.

Let’s compare the sampled voltages from the ideal model with the model derived from the product specifications.

### Ideal Versus Real-World

The ADS8326’s input drive circuit in Figure 4 (U1, R1, and C2) is properly designed, following the principles in Reference 33. To test the model, however, we replaced R1 with a 10k resistor and removed C2, as in Figure 3. Figure 5 shows the results of running a simulation.

5. These are the simulation results from the TINA-TI test bench in Figure 4. Sample and VReset are PWL signal sources to control the switches. VM1 is the ideal held voltage, while VADC_IN is the voltage on the ADC input pin. VSH is the voltage held for the ADC to use as its input. Using TINA-TI’s waveform math, the difference (Diff) between VM1 and VSH is taken and converted to LSBs (ErrorInLSB). An improperly designed drive circuit can produce significant conversion errors!

The waveform at VADC_IN closely resembles that shown in the oscilloscope trace of Figure 4 under the same conditions. Using the test bench’s “ideal sample/hold,” we can compare what the ADC (VM1) should have captured and what is actually captured on the sample/hold cap (VSH). The difference is on the order of 5000 LSBs—not at all accurate!

Figure 6 uses the same models, but with the proper drive circuit—an op amp, a 53-Ω resistor, and a 1200-pF capacitor. The design guidelines indicate these are appropriate values for proper settling for this ADC. The difference between the ideal sampled voltage and the actual sampled voltage when the sampling switch is opened is around 0.15 LSB, which is well under the 0.5 LSB needed for acceptable accuracy.

6. Using a correctly designed drive circuit results in barely perceptible changes in VADC_IN and an error well within the 0.5 LSB required.

Both examples use a wide-bandwidth op amp to drive the ADC. In Figure 7, we have the correct RC values, but a slow op amp. The signal on the input pin to the ADC never really settles. Not surprisingly, the sampled voltage’s error is quite high.

7. It’s necessary for the driving op amp to have sufficient bandwidth, so the signal can settle properly during the sampling process. Here, a slow op amp results in extremely large errors.

The model in Figure 4 is easy to set up and provides a good test bench to verify the drive circuitry for an SAR ADC. Most of the information needed to configure the model can be found on the manufacturer’s datasheet. The basic model shown here addresses the issue of modeling the input load and provides an “analog output” measured at VSH.

The model in this article works well for most SAR converters. High-speed pipeline-architecture ADCs and delta-sigma ADCs have similar sampling inputs, but the models for these converters need greater sophistication. Due to their higher speed, input pin parasitics need to be included in the model to assure accuracy.

In the next article, we’ll look at modeling the reference input. It might surprise you that it’s more-complicated than modeling the signal input!

### Acknowledgements

Thanks to Miro Oljaca and Matt Hann for their contributions to the development of this model.

### References

1. Downs R., “With Today’s Design Tools, You Don’t Have To Copy Your Father’s Schematics,” Electronic Design, December 16, 2011.