Makers of wireless infrastructure equipment and cellular handsets are constantly pressured to beef up performance while cutting the size and cost of their systems. The emerging third generation (3G) of mobile communications applications is only adding to the stress. It's not surprising that designers of such equipment are always exploring newer techniques and low-cost alternatives. This is especially so in the RF power arena, a critical communication-system function that enables the signal to reach all the nooks and crannies in a communications cell.
In the 900-MHz to 2.4-GHz spectrum, power-amplifier designers are tapping recent advances in silicon-based lateral-diffused MOS (LDMOS) power transistors to create new solutions as viable alternatives to bipolar junction transistors (BJTs), gallium-arsenide (GaAs) FETs, and other heterojunction structures. LDMOS power transistors have improved in efficiency, linearity, peak-power capability, and cost-per-watt performance, as well as matched input/output impedances for easy implementation.
Unlike others that require mixed voltages, these power transistors offer the benefit of using a single 28-V supply. In reality, the silicon-derived LDMOS structure has been refurbished to vie with existing power-amplifier solutions employed in wireless infrastructure applications. Similar movement also is underway in the low-voltage sector for cellular handsets.
Though LDMOS technology has progressed substantially in the last few years, its efficiency is still trailing behind GaAs transistors at higher frequencies and higher power levels. Moreover, bias-current drift continues to haunt the technology.
As LDMOS transistors push bipolar transistors out of wireless infrastructure sockets, they're poised to compete head-on with GaAs solutions in the 2.0- to 2.4-GHz spectrum. Efforts are in progress worldwide to boost the efficiency of the LDMOS structure at peak-power levels of over 100 W and frequencies of 2 GHz and above, while ensuring very low drift over time and guaranteed reliability.
Key proponents of LDMOS technology continue to address the problems at the process and circuit levels. For instance, a startup known as Xemod has developed a process that solves the gate-drift problem for LDMOS transistors that can deliver 120 W of peak output power. Also, Motorola is tapping its optimized fifth-generation (HV5) process technology to see another 5% boost in power efficiency at RF frequencies, while targeting less than a 5% gate threshold-voltage (VGS) drift over a 20-year period with no burn-in.
Likewise, Philips Semiconductors and Ericsson are exploiting gold-top metallization for long-term reliability to guarantee very high mean-time-to-failure (MTF) rates for their respective LDMOS parts. Furthermore, they are enhancing the gate-drift characteristics of the device with improvements in the process technology. UltraRF, a semiconductor spin-off of RF power-module manufacturer Spectrian, is similarly focusing on refining oxide processing to alleviate the threshold drift issue associated with LDMOS. Others in this race include STMicroelectronics, Hitachi, RF Micro Devices, and Stanford Microdevices.
"Although recent improvements in device design and processing have eased the drift issue, it has not withered away completely," says Richard J. Clark, Xemod's founder and vice president of product development. According to Clark, "To minimize the effects of hot-carrier injection in LDMOS power transistors, Xemod has concentrated on shaping the area under the gate, as well as incorporating a chemically enhanced gate-oxide formation technique."
It's the optimum combination of device structure and gate-oxide processing that has enabled the company to obtain desired results, Clark notes. Implementing its improved LDMOS devices, Xemod is readying power modules with up to 120 W of output at frequencies as high as 2.1 GHz for high-volume PCS and cellular base-station applications.
To simplify the use of its power modules, Xemod has ensured that the modules offer matched input and output impedances at 50 Ω. They include all of the bias and correction circuitry needed to amplify a fraction of 1 W of input power to over 100 W of output power at RF frequencies for wireless networks. Each module offers a high ratio of peak to average-output power. This ratio is an important specification for the new generation of cellular base stations, based on the W-CDMA standard, that must provide high peak power to handle multiple carriers concurrently. "Because LDMOS exploits larger CMOS wafers, it can provide a cost advantage over its close rivals by almost 50%," says Clark.
Leveraging advances in MOS design and process technology, Motorola's latest n-channel LDMOS parts, operating in the 2.1- to 2.2-GHz range, have progressed in linearity, efficiency, VGS drift, and intermodulation distortion (IMD) to meet the ultra-linear power amplification needs of the W-CDMA and UMTS standards. In fact, IMD parameters are gaining attention on data sheets, as makers begin to provide these curves to describe the transistor's performance. As users begin to explore this technology's potential, suppliers are providing IMD-versus-power graphs under a variety of bias, frequency, and input/output power conditions to show a device's true linearity performance.
Interestingly, Motorola's Semiconductor Products Sector (SPS) intends to make the drift a non-issue in future LDMOS releases. With proper drain engineering and an optimal doping profile, "Motorola aims to drive drift performance below 5% over 20 years without burn-in," says Lynelle McKay, RF operations manager for Motorola's Wireless Infrastructure Systems Division. "At this level, it will become a non-issue."
Presently employing a fourth-generation (HV4) process technology, Motorola's RF LDMOS devices guarantee less than 10% VGS drift over a period of 20 years. In short, Motorola has a rigorous drain-engineering effort to reduce the peak electric field and move it away from the surface, while simultaneously cutting RDS(on) without compromising the breakdown voltage or ruggedness (Fig. 1).
"Our device development strategy is driven by two primary goals—improved performance (higher power, higher efficiency, increased PSAT/mm, and improved linearity) and enhanced reliability (reduced HCI, better ESD protection, and ruggedness)," notes Wayne Burger, RF LDMOS device manager for Motorola's Wireless Infrastructure Systems.
Techniques for accomplishing these goals focus on "reducing device parasitics, increasing PSAT/mm, and improving source/drain region design," says Burger. "Gate-oxide thickness and gate length are two key parameters that impact both reliability and performance of the RF device.
"Consequently," he continues, "the selection and optimization of the final gate oxide and gate length involves extensive channel engineering to improve salient device parameters like leakage, hot-carrier injection (HCI), the shape of the transconductance (GM) curve, the cut-off frequency, and the maximum operating frequency."
Aside from these refinements, the next-generation process also implements techniques to reduce device parasitics, including various terminal capacitances such as CGD, CDS, CGS, RDS(on), and RG. To explore new device structures and shorten platform development cycle times, Motorola developers are leveraging predictive (simulation) engineering. Significant development work is in progress to extend existing small-signal ac simulation tools to the large-signal RF domain, and to improve predictive capability for large-signal RF circuits.
Concurrently, Motorola is pushing the power-density bar of its LDMOS transistors to higher levels. By lowering the thermal resistance of the die by 15% to 30% in the latest parts, the manufacturer has attained 125 W of peak power from the flagship member of the new RF LDMOS line.
To improve the transistors' power density using the HV4 process, Motorola thinned the die. The latest parts, such as the MRF21125 and MRF21180, will be fabricated using a 6-in. wafer that is only 4-mils thick. Present thickness is around 6 mils. As a result, the MRF21125 will be able to deliver 125 W of peak power and 20 W of average power from an existing footprint of the conventional package.
"With a peak-to-average power ratio of 8.5 dB, a gain of 13 dB, and −42 dBc third-order intermodulation distortion (IM3), the n-channel MRF21125 is designed to meet two-carrier W-CDMA requirements," says Motorola RF-applications engineer Nagaraj Dixit. For applications requiring even higher peak and average power, Motorola has developed a push-pull version. The MRF21180 offers an average power of 30 W and a peak power of 180 W with a gain of 11.8 dB over the frequency range of 2110 to 2170 MHz. Both of the new LDMOS members based on the HV4x4 platform are slated for release at the upcoming Wireless symposium in San Jose, Calif.
Versions exploiting the fifth-generation HV5 technology also are in preparation (Table 1). With satisfactory results from 4-mil thick die, the plan now is to further slice the die's thickness to 2 mils and below. Another thrust is the development of device platforms beyond the conventional 26-V discrete arena. Toward that end, Motorola is developing a 50-V platform for frequencies up to 2 GHz, as well as multistage, high-power integrated power amplifiers with enhanced functionality.
Plastic Packages Used Meanwhile, Motorola also has developed plastic packages for these RF transistors. Dissipating tens of watts of power requires ceramic and other special packaging materials to handle heat and related thermal issues, adding to the cost of the transistor. By packing these new RF power devices in low-cost plastic packages, Motorola has mitigated the cost burden while making it easier to use them from design and assembly standpoints. According to the company, while plastic packaging drives LDMOS devices into mainstream manufacturing, it also lowers the dollar-per-watt cost by over 50%.Though the initial move is to encase lower-power RF LDMOS transistors used as drivers for the output power-amplifier stages in the 900-MHz range, Motorola's engineers plan to extend that capability to the 1- to 2-GHz range in 2001. For that, Motorola's researchers are exploring new packaging materials with a lower dielectric constant and a higher glass-transition temperature.
In fact, Motorola has adopted a multipronged strategy for LDMOS technology. In addition to high-voltage power-amplifier solutions for infrastructure applications, the firm has taken the low-voltage route for telephone handsets. With the low-cost advantage of discrete LDMOS technology, the company is readying parts for 900-MHz GSM applications.
"The efficiency and gain of low-voltage LDMOS is slightly under GaAs solutions, but the cost is lower," says Mike Civiello, director of marketing for wireless transmitter solution operations at Motorola. The firm is now extending the frequency range of its low-voltage parts to 2 GHz with better power density and a few percentage points of improvement in efficiency. In the works are LV4 and LV5 processes for 3-V single Li-ion cell designs (Table 2). While discrete LDMOS transistors based on the LV4 process are rolling out, the LV5-based devices are slated for release this summer.
Philips Semiconductors is working to extend the cut-off frequency of its second-generation LDMOS power transistors up to 3.5 GHz with much higher peak power and better linearity, while ensuring that devices meet 10% drift characteristics without burn-in. Developers at Philips also are concentrating on further improving the drift over time. The current trend is to achieve 10% drift over 20 years after burn-in for units above 2 GHz. However, Philips is aiming to improve that specification substantially by minimizing HCI and shielding the FET's gate and drain (Fig. 2).
With such improvements, Philips hopes to cut that drift down to 3% to 5% over 20 years without burn-in, says Korne Vennema, manager for the company's RF Applications Laboratory. "This isolation technique lowers feedback capacitance, thereby boosting the gain and linearity of the device," Vennema notes.
Additionally, Philips is employing gold-top metallization for better reliability. Engineers there tested the same device with aluminum and gold metallization and found that gold is superior in terms of median time to failure (MTF) for electromigration (Fig. 3).
Internal Matching Inherently, LDMOS transistors come with very low input and output impedances of about 2 to 3 Ω. To simplify the use of these power transistors in real-world applications, the devices are matched internally using LC matching networks inside the package. This internal matching further improves the gain performance of the device, Philips claims. Philips intends to sample its second-generation LDMOS power transistors to key customers in the second half of this year.
In this race to cost-effectively generate more RF power, Stanford Microdevices has refined the LDMOS design to achieve higher output power at 2.4 GHz. The company is talking about offering 60 W of continuous power and greater than 100 W of peak power at 2.4 GHz from a single-ended LDMOS device.
"As you go higher in frequency, the output power drops off rather quickly" says Gary Gianatasio, vice president and general manager of wireless infrastructure products at Stanford. "Our goal now is to achieve 70-W continuous power at 2.4 GHz from an LDMOS transistor," he adds. Since they use an outside foundry service for their high-performance devices, Stanford's developers employ modeling in the design to predict characteristics in the final product.
Powering base-station transmitters at 2.4 GHz also is UltraRF's forte. Like others in this fray, UltraRF is preparing LDMOS devices that can operate with reliability up to 2.4 GHz. Its parent company, Spectrian, is deploying these transistors to offer RF power-amplifier modules for base-station transmitters.
Currently, packaging and power density are two main areas of interest for UltraRF for next-generation RF LDMOS devices. To reduce costs in future systems, the maker is exploiting the cost and high-density benefits of low-temperature co-fired ceramics (LTCC). John Quinn, UltraRF's vice president of marketing and product development, says that the LTCC technology affords equivalent dollars-per-watt performance to plastic packaging, while providing the inherent quality and reliability of ceramics.
Wring Out Power Through Balance Extracting maximum power out of a given die size also is the thrust at UltraRF. To achieve that, designers there have developed a unique die architecture that permits balanced power distribution and combining of power without resorting to a two-layer metal system. Using this proprietary architecture, it is possible to scale small device structures producing large die without loss in critical parameters, such as gain and efficiency, Quinn explains. Presently, it offers single-die 1-GHz LDMOS at 90 W (CW) output, and single-die 2-GHz LDMOS at 60 W (CW). All of its devices utilize gold metallization for the highest RF performance and maximum MTF.Increasing output power, minimizing voltage-threshold drift, and reducing hot-carrier injection through process enhancement is on Hitachi Semiconductor's design board. From about 110 W peak power at 2.14 GHz, Hitachi is planning to increase to 150 W by the middle of this year. Also, it is investigating techniques to substantially improve the hot-carrier effect of its 2-GHz parts. To guarantee the specifications on its data sheets, Hitachi subjects its devices to accelerated life testing.
Meanwhile, university laboratories around the world continue to modify the RF LDMOS structure to squeeze more juice out of a smaller die. And, they're doing so with much greater reliability. To boost output-power capability by roughly 35%, researchers at the Institute of Microelectronics and National University of Singapore have jointly developed techniques to cut large parasitic feedback capacitance by 40%, as well as hot-carrier injection by 70%. These results were detailed at the last International Electron Devices Meeting (IEDM).
Both the feedback capacitance and hot-electron injection into the gate oxide are major obstacles in conventional LDMOS devices. While the parasitic feedback capacitance limits the device's power-gain characteristics, the hot-carrier effect degrades the structure's current-carrying ability. The hot-carrier effect becomes more prominent at high voltages and reduced gate lengths. Since the LDMOS device is utilized in RF power amplifiers, the gate and drain are biased at high voltages, forcing the device to operate at high electric field while drawing high current. To achieve operations over 2 GHz, the gate length must be shrunk. Both of these conditions contribute significantly to hot-carrier degradation.
To overcome these drawbacks, Singapore researchers have modified the drain sector. By implementing a two-step lightly doped drain (LDD), they have shown that the parasitic feedback capacitance (CSI) and the on-resistance can be cut simultaneously. Additionally, a thermal oxide spacer is used to minimize gate/LDD1 overlap to cut COX, another contributor to feedback capacitance. This combination of a two-step LDD with an inherent spacer enables the developers to slash both COX and CSI to obtain nearly a 40% reduction in overall parasitic feedback capacitance, according to the University of Singapore paper given at IEDM.
Similarly, to improve the power-added efficiency (PAE) of the silicon LDMOS transistor at low supply voltages, researchers at Hitachi ULSI Systems Co. have scaled the MOSFET's gate width. By implementing a thin-gate bird's-beak technique to keep oxide thickness to 10 nm, the researchers achieved a 60% PAE at 1 W of output power and 2-GHz operation.
LDMOS devices have moved up the performance ladder in the last few years to displace bipolar and challenge GaAs devices in RF power-amplifier solutions for wireless base-station infrastructure applications. However, they're still trailing behind GaAs in efficiency and gain. Lower cost certainly is a big advantage with silicon LDMOS. To maintain its edge and address the cost issues, GaAs suppliers are migrating to larger wafers.