Power-Efficient Alternatives
New low-power, multicore digital signal processors (DSPs) for voice and video applications are scalable in terms of channel processing density. This scalability enables them to be deployed across the network from lower-density access points to the higher-density core network infrastructure.
These DSPs are built on a fundamentally power-efficient architecture using a highly power-efficient asynchronous processor. The power efficiency comes from the asynchronous design of the core itself. By removing the clocks and the synchronizing registers in the processor core and replacing them with simpler logic-based synchronization methods, three things happen:
• The silicon area of the DSP core is reduced.
• The power and wiring from the clock and register infrastructure is removed.
• The cumulative effects of reducing the area removing the clock yield even greater power reductions.
The net result is a high-performance device capable of transcoding, for instance, up to 20 CIF or 70 QCIF video streams or up to 480 voice channels. This level of channel density is achievable within a power footprint of 1.9 W.
Compare this density to that of a standard server-class x86 processor. Within an approximate processing/power envelope of 150 W, typical QCIF transcoding density is around 150 video streams for a pure x86 setup.
Even when considering the implementation-specific details of adding DSP resources into a system, the possible power and efficiency gains are very large. Figure 2 shows the power consumption for x86 versus DSP transcoding.
The Future
In response to the predicted and obviously growing demand for mobile and Internet-based video services, DSP designers and video server, streamer, and gateway manufacturers have to engage the new paradigm of a highly power-efficient mobile video platform.
The new platform must be designed from inception to deal with the high processing demands of video transcoding and remain flexible enough to deal with ever-changing video resolution, frame rate, and codec standards. This new paradigm now provides manufacturers of video transcoding equipment an alternative to power-hungry x86-based processors and even a power-efficient alternative to standard DSPs used by those who have already recognized the benefits of moving away from x86s.
Although the shift to a new processor can be daunting, the benefits are groundbreaking. For example, compared to a typical server-class dual quad-core Xeon setup, the new generation DSP can very easily provide a gain of approximately 15 times in channel density without increasing power consumption. Alternatively, the same power efficiency can be used for simple power reductions greater than 60% without sacrificing channel density.
Once these processors are deployed in video transcoding systems, the benefits of power efficiency immediately move outward to the system and provide greatly reduced operating costs, higher levels of achievable channel density and scalability, and overall system reliability.
Imagine that those equipment manufacturers who use new low-power, high-performance DSPs can easily position these power benefits at the next level to their end customers. The power and channel density gains simply mean that more transcoding capability can fit into a greatly reduced area. Even achieving a more modest approximately tenfold power-density gain could mean a simple tenfold reduction in the total number of servers required in a real deployment. The power-savings possibilities (based on complete server power consumption) are enormous.
Beyond the tangible and measurable benefits, simply being able to produce a more power-efficient product is a common goal at all levels of the industry—for sustainability, for cost containment, and for customer satisfaction.
John Fry, director of business development, has more than 15 years of programmable DSP experience in the video and communications industry. Prior to joining Octasic, he worked as director of customer applications for Stretch Inc. Earlier in his career, he was a senior DSP marketing manger at Altera and a senior R&D engineer at Snell & Wilcox. He holds a BEng in communications systems engineering from the University of Portsmouth in the U.K.