GETTING PHYSICAL
After simulation runs are used
to iron out performance issues, the next step is to lay out
the circuit for physical prototyping. A layout ensures that
the circuit performs according to design specifications. It
also verifies that the board outline matches the design
form factor. "Here's where you get into co-design with the
mechanical engineers," says Wiens.
The layout stage is the physical manifestation of the
interconnects between components defined by the
schematic. The task is performed with place-and-route
tools provided by any number of EDA vendors. All of these
tools bring varying amounts of automation to the table,
but that's a double-edged sword.
"Designers need to use judgment on when to use manual layout and when to go automatic," says NI's Mistry. "If you're placing critical components, or when you must
place a connector near the edge of the board, you can't
give the automatic placement capability the ability to
override your decisions."
Hopefully, some forethought will be given to signal-integrity issues when it's time to do the layout. This is the
stage at which it must be dealt with in earnest. "The general rule of thumb is that if your signal takes more than
one-third of its rise time to get to its destination, then you
have a potential signal-integrity problem in that path,"
says Rob Irwin, product marketing manager at Altium.
CONSTRAINTS ABOUND
Many challenges surround PCB layout. Primary among them is ensuring adherence to constraints. "Today's boards have a high percentage of nets with very complex constraints," says Mentor's
Wiens. These constraints can be meant to address signal
integrity, manufacturing concerns, electromagnetic-interference issues, thermal issues, or combinations thereof.
"Layout designers have to comply with these rules, but
they can conflict at times. The designer has to be highly
proficient and aware of what all of the constraints mean,"
says Wiens.
Aside from design constraints, many factors endemic
to today's component technology complicate PCB layout.
For one, advanced semiconductor packages such as chip-on-board (COB, or bare die with wire bonds) can
make routing a nightmare.
In addition, today's microdense packages can have
more than 2000 pins at pitches of less than 0.65 mm.
This could wreak havoc in terms of managing I/Os and
signal speeds. The creation of escape routing from such
packages is tricky, to say the least.
Design with programmable logic is yet another challenge
for PCB layout. Some high-end board-design suites, most
notably those from Altium and Mentor Graphics, have tight
links to those vendors' FPGA design tools and can handle
integrated design of the FPGA and the board itself.
"When you have a large FPGA, the pinout tends to come
from the FPGA designer, who creates that pinout without
much regard for the board layout," says Altium's Irwin. "People are only now beginning to realize that the FPGA, with its
programmable I/Os, is a routing resource in and of itself. It's
a lot easier to change the FPGA to suit the board layout than
it is to change the board to suit the FPGA's I/O setup."
FINAL CHECKS
The last stage before releasing a PCB
to manufacturing is a final verification run. Signal integrity
and timing must be checked to ensure that signals reach
their destinations on time and with sufficient quality. This is
the juncture where collisions between design constraints
will reveal themselves and tradeoffs are made.
"One of the biggest challenges is trying to move these
final verification steps to earlier stages of the design
process," says Mentor's Wiens. "A key to being able to do
so is having better constraints. If you can perform analysis while specifying constraints during design creation,
the constraints will be improved."
At this stage, a final comparison is made between the
design specifications and its real-world behavior. The performance of the physical prototype is carefully evaluated
so that the effects of the system's operational environment can be well understood and any necessary modifications made.
GETTING IT MADE
Intimately tied with final verification is manufacturing preparation. Hopefully, the members of the design teams have had sufficient communication with the manufacturing house throughout the entire
process so they understand the manufacturer's capabilities and limitations.
Manufacturing data must be generated, including all
pertinent documentation regarding fabrication, assembly, and test. The panel design is also specified to fabricate them efficiently, minimizing costs. In addition, the
manufacturing data must be verified, giving designers
one last chance to catch errors.