Full article begins on Page 2
High-speed digital buses continuously evolve. Not only are they faster, but they're chang-ing how a system clocks data. To improve data throughput, emerging synchronous digital buses are sending data multiple times per cycle via an array of clocking schemes. High-speed synchronous data transfers are becoming more common: Synchronous clocking modes that began life in high-end computing equipment are now trickling down to mid-market products. Thus, there's a greater demand for labor-saving digital troubleshooting solutions.
One of the most productive tools for debugging synchronous systems is the logic analyzer. When properly equipped, it can directly capture high-speed synchronous data. At the heart of the high-speed synchronous data-acquisition challenge, though, is the requirement for great flexibility in clocking and triggering.
Digital system designers have learned that in conventional parallel-bus architectures, brute-force increases in clock rate can yield diminishing returns. In response to this lesson, digital architects have devised a number of innovative clocking approaches, including "double-pumped," "quad-pumped," and "source-synchronous." This article defines and explains how these different approaches work and how to capture the right data at the right time.
One approach that gets particular focus is source-synchronous. Here, dedicated strobe signals are used instead of, or sometimes in addition to, a normal clock pulse. This makes acquisition inherently more complex. Yet despite the fact that several more steps are involved in its setup, as opposed to the other approaches, a dedicated source-synchronous mode makes the setup process straightforward. The "pyramid" step approach is detailed in the article.
Full article begins on Page 2
Full article begins on Page 2
High-speed digital buses continuously evolve. Not only are they faster, but they're chang-ing how a system clocks data. To improve data throughput, emerging synchronous digital buses are sending data multiple times per cycle via an array of clocking schemes. High-speed synchronous data transfers are becoming more common: Synchronous clocking modes that began life in high-end computing equipment are now trickling down to mid-market products. Thus, there's a greater demand for labor-saving digital troubleshooting solutions.
One of the most productive tools for debugging synchronous systems is the logic analyzer. When properly equipped, it can directly capture high-speed synchronous data. At the heart of the high-speed synchronous data-acquisition challenge, though, is the requirement for great flexibility in clocking and triggering.
Digital system designers have learned that in conventional parallel-bus architectures, brute-force increases in clock rate can yield diminishing returns. In response to this lesson, digital architects have devised a number of innovative clocking approaches, including "double-pumped," "quad-pumped," and "source-synchronous." This article defines and explains how these different approaches work and how to capture the right data at the right time.
One approach that gets particular focus is source-synchronous. Here, dedicated strobe signals are used instead of, or sometimes in addition to, a normal clock pulse. This makes acquisition inherently more complex. Yet despite the fact that several more steps are involved in its setup, as opposed to the other approaches, a dedicated source-synchronous mode makes the setup process straightforward. The "pyramid" step approach is detailed in the article.
Full article begins on Page 2