The data stream from the modulator is fed to a cascaded multistage digital filter, designed to optimize phase and amplitude performance at the lowest possible power dissipation. Future family members will offer resolutions ranging from 12 to 18 bits and sample rates in hundreds of megahertz. Up to 80-Msample/s rates (at 14 bits) are anticipated, with an oversampling clock rate of approximately 1.3 GHz.
A key ingredient in Xignal's ADC is a high-performance clock source integrated on-chip with the core. The only external component needed is a low-cost crystal, parallel-connected to the clock input. The clock is connected to a high-performance PLL block that uses an on-chip, LC-tuned circuit to create a high-Q resonator, creating a very precise clock source.
It's also possible to use an external clock to drive the ADC. In that case, any high-frequency jitter from the external clock tree will be removed, provided its jitter falls outside the 350-kHz PLL bandwidth of the jitter cleaner circuit. A better idea, however, might be to route the on-chip precision clock to external circuits, using it as the system reference clock.
The data stream from the modulator is fed to a cascaded multistage digital filter, designed to optimize phase and amplitude performance at the lowest possible power dissipation. Future family members will offer resolutions ranging from 12 to 18 bits and sample rates in hundreds of megahertz. Up to 80-Msample/s rates (at 14 bits) are anticipated, with an oversampling clock rate of approximately 1.3 GHz.
A key ingredient in Xignal's ADC is a high-performance clock source integrated on-chip with the core. The only external component needed is a low-cost crystal, parallel-connected to the clock input. The clock is connected to a high-performance PLL block that uses an on-chip, LC-tuned circuit to create a high-Q resonator, creating a very precise clock source.
It's also possible to use an external clock to drive the ADC. In that case, any high-frequency jitter from the external clock tree will be removed, provided its jitter falls outside the 350-kHz PLL bandwidth of the jitter cleaner circuit. A better idea, however, might be to route the on-chip precision clock to external circuits, using it as the system reference clock.