1.5-Bit Stages In Pipeline ADCs

Use of pipeline analog-to-digital converters (ADCs) continues to expand, both as standalone parts and as embedded functional blocks in system-on-a-chip (SoC) ICs. They boast acceptable resolution at high-speed operation and can be integrated onto relatively small die area. Driven by IC chip cost factors, many commodity CMOS-technology SoCs now include embedded pipeline ADCs.

Pipelined converters attain their final resolution through a series cascade of lower-resolution stages. For example, a 12-bit converter could be a cascade of four 3-bit stages. Most engineers are comfortable with the basic concepts of a 3-bit flash ADC stage. However, the 1.5-bit stage also is used extensively, despite the fact that its characteristics and advantages are less widely known.

Pipeline ADCs consist of a series of stages that are isolated by sample-andhold (S/H) buffers. The stages work concurrently. The first stage operates on the most recent sample, while the following stages operate on analog remainder voltages, called residues from previous samples.

Because the stages work simultaneously, the number of stages used to obtain a given resolution (e.g., 12 bits) isn't constrained by the required throughput rate (e.g., 20 Mbits/s). The stages can be designed, among other factors, to minimize die area.

A consequence of multistage concurrent operation is latency, meaning delay. The output code for a given sample isn't obtained until a number of clock cycles later. Latency isn't considered to be a problem in many applications.

Figure 1 shows a block diagram of a general pipelined ADC with M stages. For every stage, there's a S/H, a low-resolution ADC, a low-resolution digital-to-analog converter (DAC), a subtracter, and a controlled gain amplifier.

Each stage samples and holds the output from the previous stage. The held input is converted into a low-resolution digital code by the ADC, and then back to analog by the DAC. The DAC output is subtracted from the held input, and the difference is amplified to produce an output residue voltage that's passed to the next stage.

In general, the amplification corresponds to the resolution of the stage to use the full voltage range available. For example, a 3-bit stage would have an amplification of 8. The amplifier can be placed either in front of, or following, the subtracter.

1.5-BIT STAGES
For high-speed converters, there's an advantage to minimum stage resolution. It minimizes the required interstage gain, which in turn maximizes bandwidth, since gain-bandwidth is a constant for a given technology. This factor is particularly important for parts made using a cost-effective commodity CMOS wafer-fabrication process, as maximum achievable speed is required from critical circuit blocks such as operational amplifiers.

Assume symmetrical reference voltages of ±VREF. The minimum possible stage resolution (and maximum bandwidth) of 1 bit would place an analog decision level midway between the reference voltages—that is, at ground. The amplifier would have a gain of 2.

A 1.5-bit stage is a 1-bit stage into which some redundancy is built to provide a large tolerance for component tolerances and imperfections. A digital correction algorithm later eliminates the redundancy. A 1.5-bit stage is actually a stage that represents approximately 1.5 bits.

The 1.5-bit stage uses two symmetrical analog comparison levels, VH and VL, instead of one (Fig. 2a). The amplifier has a gain of 2. Choice of voltage levels VH and VL isn't critical, but because of the following gain of 2, they must lie within the range of -V_REF/2 and +V_REF/2.

Allowing for circuit imperfections to be corrected by the digital correction algorithm, V_H is usually in the range 0.2 V_REFHREF. A common choice is V_H = 0.25 V_REF and VL = -0.25 VREF. The 1.5-bit configuration holds an advantage in that there's no analog decision level or trip point at mid-range, which benefits low-signal-level operation.

The operating voltage range is divided into three sections: High (H) above V_H, Mid (M) between V_H and VL, and Low (L) negative of V_L. This system is known as Redundant Signed Digit (RDS) because the High range was originally tagged as +1, Mid range as 0, and Low range as -1. Table 1 lists summary information about the 1.5-bit stage configuration.

The stage low-resolution ADC comprises two comparators plus some simple encoding. The ADC output consists of two bits—B1 and B0. This is the initial digital output, before code conversion and error correction. The output codes are 00, 01, and 10 for V_IN in the L, M, and H input ranges, respectively. The DAC outputs are -V_REF, 0, and +V_REF for V_IN in the L, M, and H input ranges. The analog residue voltages out of the stage after subtraction are:

Figure 2b shows the stage V_OUT/V_IN transfer function, which is highly nonlinear, for V_H = 0.25 V_REF and V_L = -0.25 V_REF.