When I report on new products,
I usually avoid claims that chips are “so
many percent” better in some way than
their competitors. That’s because specsmanship
is a constant game of leapfrog.
Sometimes a focus on specs can lead to an
awkward situation.
For example, Texas Instruments and
National Semiconductor demonstrated
the perils of dueling specifications last
January by announcing new analog-todigital
converters (ADCs) for the same
application space (high-end medical
imaging) with nearly identical groundbreaking
performance within days of
each other (Fig. 1).
A TIE FOR “BEST”
So I’m calling that one a tie. I felt sorry
for the folks at TI, who announced their
chips first. Their products also substantially
reduced power consumption compared
to what had been out there. Still,
by using a brand-new topology, National
squeezed its power by that much again.
Number-wise, it was a case of a third of
a third of what was already a very small
quantity, but National earned the right to
crow—and that’s marketing.
Those two chips were TI’s pipeline
ADS5281 and National’s continuoustime
(CT) delta-sigma ADC12EU050.
Both are 12-bit, 50-Msample/s
ADCs, though TI promised a future
65-Msample/s version. TI also claimed 70 dB full-scale at a 10-MHz IF, while
National claimed 70 dB at 3.5 MHz.
Power was the big issue. TI’s part drew
64 mW, National’s 44 mW. Pricewise,
though, TI came in at $60 (in sample
quantities), and National at $64. Packaging
for the National part was a millimeter
bigger in each horizontal direction.
With that tight a race in specifications,
it became more interesting to
examine implicit differences between
the pipeline and CT delta-sigma architectures.
Although CT was previously
used in delta-sigmas integrated into
more complex chips, the National chip
was the industry’s first “discrete” commercial
CT delta-sigma ADC. That had
both plusses and minuses.
National took advantage of the oversampling
architecture’s low-pass, brickwall,
anti-aliasing filter to obviate the
need for an external AA filter. Also,
the CT architecture meant the IC had
an easy-to-drive, purely resistive input
stage that required no sample-and-hold
amplifier. On the other hand, National
had to overcome the CT architecture’s
traditional susceptibility to clock jitter
with an integrated phase-locked loop
(PLL) and voltage-controlled oscillator
for clock conditioning.
Meanwhile, TI’s engineers were busy
building in a low-frequency noise-suppression
mode to eliminate 1/f noise.
As a result, signal-to-noise ratio (SNR)
improved by up to 4.2 dB over a 1-MHz
band in baseband and time-domain
applications. TI also included overloadrecovery
circuitry for ultrasound applications
and programmable gain.
DATA CONVERTERS:
INTERFACE DESIGN
Back in April, Linear Technology
focused on the communication between
high-speed ADCs and FPGAs with its
LTC2274 16-bit, 105-Msample/s ADC,
which offered a single, self-clocking, differential-
pair serial interface, communicating
at 2.1 Gbits/s (Fig. 2). While lots
of ADCs have serial outputs, the trick is making them that fast. Until recently, typical serial transmission
could not be accomplished above 1.2 GHz, forcing a tradeoff
between speed or resolution of an ADC.
In 2006, the JEDEC group formulated a serial interface specification
( JESD204) that enables a high-speed serial connection
between data converters and logic devices over two wires. The electrical
layer of the specification supports code rates of 312.5 Mbits/s
to 3.125 Gbits/s across a current-mode logic (CML) pair.
This self-clocked serial data stream is encoded using 8B/10B
coding, which provides benefits over conventional serial transmission
by using a running disparity to eliminate dc imbalance in the
signal. In noise-sensitive applications, this serial interface can be
transmitted across an isolation barrier between digital and analog
circuitry. It also serves to eliminate digital feedback.
The LTC2274 is the first ADC to adopt the JEDEC serial
interface, making it compatible with many FPGA high-speed
interfaces like Xilinx’s Rocket IO, Altera’s Stratix II GX I/O, and
Lattice’s ECP2M I/O. With fewer output pins than a paralleloutput
device, the LTC2274 fits in a 6- by 6-mm quad flat no-lead
(QFN) package.
As was to be expected, Linear’s engineering team combined
high ac performance and the high-speed serial interface on the
same die. That means a 77.5-dBFS SNR and 100-dB spuriousfree
dynamic range (SFDR) at baseband. Some special features
also facilitate system design.
For high-sensitivity receiver applications, an internal transparent
dither circuit improves the ADC’s SFDR response well
beyond 100 dBc for low-level input signals. To avoid any interference
from the serial digital outputs, an optional data scrambler can
randomize the spectrum of the serial link. Serial test patterns can
facilitate testing of the serial interface. Pricing starts at $68.00.
SPEED AND ACCURACY IN MEDICINE
Analog Devices’ 2008 additions to its PulSAR family of precision
16-bit successive-approximation register (SAR) ADCs upped
the ante for speed and accuracy in that class of converter, which
targets medical MRI and digital X-ray systems.
At a 10-Msample/s throughput, the AD7626 achieved a 15-bit
effective number of bits (ENOB). That’s due to its 92-dB SNR,
which is 8 dB higher than any ADC running at that rate, regardless
of architecture.
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