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Synchronous Detection Plays A Role In Better Analog Design
Designers can use this technique to exploit delta-sigma modulation and density-domain signal processing for better performance.
Date Posted: October 01, 2009 12:00 AM
The analog section contains a band-pass filter designed with a center frequency of 7.8125 kHz and a Q of four. Its output is a 7.8125-kHz sinusoid with an amplitude of 1.15 V and a phase delay of zero. It is connected to the analog output buffer on P0.5. This is the modulated stimulus.
The ADC is set for 14 bits and uses a 4-MHz column clock. This sets the integration time to 16.38 ms or exactly 128 cycles of 7.8125 kHz. The analog part of the ADC is a ?SM. The column 0 analog comparator LUT is set to be an XNOR to modulate this ?SM density stream. A comparator is required to get the modulation signal from P0.0 to the column 1 comparator bus. A buffer is used to connect the input signal MUX to the ADC input. Software is used to connect AGND to the analog output buffer on P0.3
RESULTS
For all tests, the reference resister used was measured and found to be 10.02 kO. A Fluke 85 multimeter performed the measurement. For the first impedance test, a 15-kO resistor was measured. The following data was collected for each of the three inputs (in counts):
VHIGH = 4568 – i401 counts
VMID = 2742 – i227 counts
VLOW = 0 + i1 counts
Although this is a purely resistive measurement, there is a slightly out-ofphase component. This is because of delay in the analog path. In a production unit, the phase of the modulation waveforms would be adjusted to compensate for this. Applying this data to Equation 9 results in Equation 10.
This works out to an amplitude of 15.03 kO and a phase shift of 0.6°. When measured with a Fluke 85 multimeter, the test resister value is measured at 14.99 kO. For the second impedance test, a 1000-pF capacitor is measured. The following data is collected for each of the three inputs:
VHIGH = 4588 – i407 counts
VMID = 3812 + i1488 counts
VLOW = –1 – i2 counts
Applying this data to Equation 9 results in Equation 11. This works out to an amplitude of 20.02 kO and 89° phase shift. Equation 12 shows the capacitance value.
Delta-sigma modulation easily allows analog signals to be converted to the density domain. Density-domain signal processing and averaging ADCs allow for the inexpensive construction of synchronous detectors in particular and signal multipliers in general.