The MAX1402's input multiplexer can be set to manage three fully differential signals or five pseudodifferential signals. The multiplexer is followed by two chopper amplifiers, a programmable-gain amplifier (PGA) (with gain from 1 to 128), a coarse DAC to remove system offset, and a second-order delta-sigma converter. The 1-bit data stream is then filtered with an integrated digital filter configurable as SINC1 or SINC3. The conversion result is made available via an SPI/QSPI-compatible, three-wire serial interface.
Representing the alternative "big-D, little-a" approach, Silicon Labs' C8051F350 is the company's latest 8051-compatible MCU with an on-chip ADC. It integrates an eight-channel, 24-bit, 100-ksample/s converter with a 50-MHz CPU. Peripherals include dual 8-bit DACs and a temperature sensor. Among the on-board serial communication peripherals are UART, SPI, and SMBus serial ports.
Similarly, Microchip Technology's PIC16F684, PIC16F688, and PIC12F683 PIC-based MCUs incorporate 10-bit successive-approximation ADCs with eight-input multiplexers.
Significantly more complex, Cypress Semiconductor's pSoC family members offer a set of complex digital and analog blocks that are totally in-circuit reprogrammable. Cypress' director of strategic marketing, Nathan John, says that a pSoC IC's analog blocks may include up to four ADCs (with 6- to 14-bit resolution, selectable as pipelined, delta-sigma, and successive approximation); two-, four-, and six-pole band-pass, low-pass, and notch filters; 6- to 9-bit DACs; and PGAs.
According to John, Cypress' pSoC design tools include models for two preconfigured delta-sigma converters. One has 8-bit resolution and 643 oversampling and suits up to 32 ksamples/s. The other offers 11-bit resolution and 2563 oversampling and is usable up to 7.8 ksamples/s.
Apart from products such as Silicon Labs' chip, which is more of an MCU with an ADC peripheral, and Cypress' pSoC structured ASICs, most chip makers deliberately limit the digital content of their AFEs. Analog Devices' product manager Curt Wise and senior applications engineer Paul Hendriks say there are multiple reasons for steering clear of a full system-on-a-chip (SoC) implementation. First of all, process technologies could be best suited for analog but not digital. Moreover, as chip designs move from older to newer processes, the silicon real estate taken up by the analog part of the chip doesn't shrink as fast as the digital territory.
Finally, combining too high a degree of digital and analog functionality on the same die in a cutting-edge process technology increases the risk that the first spin of the new design won't meet spec. That would mean another spin and additional mask charges. In an application-specific AFE, the risk can only be accepted if the system requirements for data-converter performance are modest and the potential sales volume is high (tens of millions of units shipped per year).
The cable modem market would then qualify for the full SoC treatment. But in broadband wireless and the emerging powerline communications market, relatively modest potential sales volumes and the need for high converter performance dictate "big-A, little-d" chip partitioning. (Streaming high-definition TV, for example, requires on the order of 70-Mbit/s throughput.) These AFEs are built on mature process technologies—0.13 or even 0.18 mm. They consist of primarily analog functionality with only an appropriate amount of digital functionality. The system's digital heavy lifting takes place in a separate digital chip built on a more advanced process technology.
So in wireless applications, precisely how much digital functionality is generally added to the data-conversion function in an AFE? Wise and Hendricks note that in the transmit channel, there will often be a digital interpolation filter ahead of the DAC. Interpolation increases the DAC's conversion rate, and the higher the conversion rate, the simpler the anti-aliasing filtering required on the DAC output.
Building the interpolation into the AFE is relatively simple, so it makes sense to transfer that functionality there and simplify the digital host chip feeding it. It also means the interface between the chips can run more slowly, removing a potential electromagnetic-interference source.
Analog Devices' AD9862 is a dual 12/14-bit, 128-Msample/s sampling ADC with decimation filters and a digital Hilbert filter. When the filter is enabled, it implements a Hilbert transform, splitting single-channel input data into its I and Q components that can be used as part of an image rejection architecture. The complex data can then be processed further using the on-chip digital complex modulators. Some AFEs may also include direct digital synthesis and digital mixers so that signals can be upconverted in the digital domain before going to the DAC.
In the receive channel, delta-sigma conversion implicitly involves digital filtering. Delta-sigma conversion is particularly useful in narrow-band wireless applications because it provides a high level of selectivity and very high instantaneous dynamic range (see "Digging Deeper: The ABCs Of AFE ADCs" for a discussion of ADC architecture tradeoffs, p. 54).
Engineers who follow converter architectures may be surprised to find delta-sigmas used at frequencies all the way up to multi-megahertz. Historically, delta-sigmas first targeted high-resolution, slow-response applications like weight scales. Later, they were applied to audio applications. Advances in process technologies now let delta-sigmas increase the speed of the sampler core to as much as 20 Msamples/s, which pushes the effective bandwidth to 2.5 MHz, while providing as much as 16 effective bits of resolution.
On the other hand, although delta-sigma conversion is attractive in narrow-band wireless applications such as voice communication over discrete RF channels, the architecture isn't appropriate for wideband applications. Rather, successive-approximation converters are usually employed for moderate- to high-speed wideband applications in industrial control and measurement. It's now common to find 16-bit, 300-Msample/s successive-approximation converters.
They're inexpensive to implement, so pipeline converters are found in applications needing only 8- or 10-bit resolutions and up to 10-Msample/s conversion rates. Pipelines introduce latency but are silicon-efficient. Building a 12-bit converter with a latency of one would require 4095 comparators and a huge die and result in a chip drawing a lots of power.
In contrast, by converting in stages, a pipeline converter can be realized with far fewer comparators—at the cost of six or seven cycles of latency. But latency is only a potential problem in feedback-loop control systems. It's not a problem in communications systems, though, because the converter's latency is a trivial part of the sum of all the delays in the whole signal chain.
Earlier, the reasons for integrating interpolation filters ahead of DACs were discussed. Though Maxim's MAX1402 incorporates a decimation filter after its delta-sigma converter, don't expect to find one on the output of a pipelined ADC. Economically, it makes more sense to insert a surface acoustic wave filter and another filter in the analog domain when using an inexpensive ADC.