Creating reusable and portable analog intellectual property (IP) is a key trend to watch in EDA for 2009 and beyond. Finding a way to develop reusable analog IP will allow designers to build differentiated products quickly and cost-effectively.
While IP reuse methodologies are available for digital blocks due to well-structured and cell-based design characteristics, design reuse methodologies across the board could be improved. Reusable analog IP needs the most improvement, however, and offers the greatest opportunity for a high return on investment.
No efficient means of capturing or transferring analog designers’ intent is available today. With an increasing number of chips using digital and analog design, an immediate need exists for automated methods of reusing and migrating analog IP to new process technologies.
Developing reusable methodologies for analog IP is difficult because analog and mixed-signal designs are susceptible to multiple design and process sensitivities. Previous solutions have relied on techniques that require hours of brute-force simulation, limiting content size that can be ported to, or optimized for, a new foundry or technology.
Requirements for an effective analog IP reuse methodology include accelerating process migration because smaller process nodes offer reduced fabrication costs. Unfortunately, many semiconductor companies cannot invest the time to retarget their analog IP and prolong their use of older process technologies.
The foundries support an analog IP reuse methodology that will enable faster porting of designs to smaller, more cost-efficient process technologies. With more efficient analog IP migration flows, semiconductor companies could accelerate adoption of newer process technologies, enabling the creation of large analog IP libraries.