Speaking of the real world, the challenge in CDR comes from jitter and noise (Fig. 3). Both factors cause variations in the placement
of signal transitions. Jitter affects horizontal placement, and noise
affects vertical placement. Together, they introduce uncertainty in
data recovery, which is perceived as a non-zero bit-error rate (BER).
Variation in edge placement essentially is a logic threshold
problem that’s exacerbated by today’s high signaling rates and low
operating voltages. The signaling rates mean that from bit to bit, it
can be statistically guaranteed that some transitions will fall outside
the logic’s setup-and-hold requirements, and the operating
voltages squeeze logic high and low signal thresholds.
There are many ways to characterize timing variations, depending
on how you want to think about them. In addition to timing
and amplitude, jitter and noise can be further broken down into
random and deterministic categories (Fig. 4). What’s significant
about the random component of both is that it doesn’t correlate to
system operation. It must be dealt with by the system design.
“Deterministic” means that those characteristics are repeatable
and predictable. Also, their peak-to-peak values are bounded and
can usually be observed or predicted with high confidence based
on a reasonably low number of observations. Deterministic jitter
and noise have further “periodic” and “data-dependent” components.
And, jitter has a “duty-cycle-dependent” component.
Periodic jitter repeats in a cyclic fashion. It’s uncorrelated with
any periodically repeating patterns in a data stream. Rather, such
jitter is typically caused by external deterministic noise sources
like switching power-supply noise, a strong local RF carrier, or an
unstable clock-recovery PLL. On the other hand, data-dependent
jitter correlates with the bit sequence in a data stream.
Duty-cycle-dependent jitter may be predicted based on whether
the associated transition is rising or falling. This may be because
the slew rate is different for rising or falling edges, or the logic
threshold voltage is different for the two cases. These situations
are similar for random and deterministic noise, except there’s no
parallel duty-cycle-dependent situation for noise.
BER derives from time interval error (TIE), the difference
between data edges and edges of the recovered clock. To measure
BER, instrumentation can measure a data sample’s TIEs and present
a histogram of TIE values versus the number of occurrences of each
value, showing the probability of a data edge occurring at a given
time within a bit period, given that the data is sampled at that time.
A TIE bathtub curve integrates the probabilities for all values of
offset. Total jitter is the width, and the sides of the bathtub give the
bit error rate for any given sampling point within a bit interval.
The horizontal distance between the curves at a given vertical
displacement or bit error rate gives the eye opening at that BER.
As long as the sides of the curve do not touch, there is a sampling
point at which the desired bit error rate can be achieved.