CMOS ADCs Surge Past 1 GHz As VCOs Race Toward 50 GHz

As RF CMOS technology progresses into deep-submicron design rules, researchers are looking into building high-bit-rate broadband communication transceivers on a single chip using low-cost technology. That means that microwave and millimeter-wave VCOs must be first built in CMOS to get there. With that goal in mind, Bell Labs scientists in Murray Hill, N.J., realized an LC-resonator-based VCO in 0.25-µm CMOS for operation at 50 GHz (Fig. 4).

Bell's scientists say the fully integrated unit consumes less power than its counterpart in exotic compound semiconductor technologies, while providing comparable phase-noise and tuning performance (paper 23.8). Tests show that the bias condition for the VCO is set at 10 mA from a 1.3-V supply. Measured single-sideband phase noise is ­99 dBc/Hz at a 1-MHz offset from the carrier. The tuning range is around 1.1 GHz with a 2.6-V variation in tuning voltage.

The VCO incorporates on-chip spiral inductors that are optimized using electromagnetic simulators for operation at 50 GHz. As a result, the LC resonator offers a quality-factor (Q) of about 10, which leads to lower power consumption and smaller parasitic capacitance. So, impedance matching appears to be a lesser issue in this approach.

New breakthroughs in CMOS imaging also were disclosed this year at the conference. A CMOS image sensor designed at Stanford University has crossed the 1-Gpixel/s barrier using a standard 0.18-µm CMOS (paper 6.1). With an ADC per pixel, this massively parallel digital pixel sensor can continuously output 10,000 frames/s at 8 bits/pixel to achieve a new milestone in image acquisition speed. This 352- by 288-pixel sensor uses 37 transistors for each of its 9.4- by 9.4-µm pixels.

Image sensors are incorporating more and more signal-processing functions on-chip, transforming themselves into image processors. Researchers at NEC Corp., Kanagawa, Japan, signal this trend with the design of a high-density CMOS image sensor that implements three additional signal-processing function modes: wide dynamic range, motion detection, and an edge-extraction mode (paper 6.6). Small pixel size and real-time operation are achieved by a four-transistor-pixel scheme and column-parallel on-chip analog operation.

These enhancements indicate that image sensors are relentlessly pursuing the silicon feature-size reduction path for low-cost system-on-a-chip (SoC) solutions. This will allow them to serve highly competitive consumer markets.