Some applications require both a hot-swap circuit to limit inrush currents and a linear regulator to maintain a constant output voltage from minimum to maximum load current. To compensate for the voltage drop (VPCB) across the trace resistance of the pc board at full load, the input voltage supply is typically adjusted upward by an amount equal to the trace drop. For example, if VOUT = 3.3 V, Load = 10 A, and the pc-board trace resistance = 40 mΩ, the input supply must be set at 3.7 V [3.3 V + (10 A × 0.040 Ω)]. Unfortunately, unless a linear regulator is used, the output voltage will now vary from 3.7 V at zero load to 3.3 V at full load.
The schematic shows such a hot-swap linear regulator circuit based on an LTC1422 hot-swap controller (U1) and an LT1431 program mable reference (U2) (Fig. 1). After power is applied to VIN, U1’s ON pin is pulled high. The GATE pin is pulled low with a current sink capability of 10 mA, and MOSFET Q1 remains off. At this point, the output is 0 V and, therefore, U1’s FB pin also is 0 V. The FB pin is the non-inverting terminal of an internal comparator. Because the input to the comparator is below the internal 1.232-V reference, the —RE —SET pin (the output of the internal comparator) is held low. After one timing cycle (given by 1.232 × C3/2 µA), U1’s GATE pin begins sourcing 10 mA. Also, the 12-V supply connected to the GATE pin through R3 sources 1.2 mA into C1, charging C1 through R1.
For hot-swap applications, R1 and C1 slow down the gate rise time to limit inrush current. As the gate voltage rises to approximately 2 V (one gate threshold voltage), Q1 starts conducting and the output voltage rises (Fig. 2). As the output voltage rises above 1.232 V, —RE —SET switches to a high impedance state and R1 and C1 are disconnected. This allows the gate voltage to rise and fall quickly for transient loads (Fig. 3). As the output voltage rises to 3.3 V, the REF pin on U2 reaches approximately 2.5 V. This forces the output of U2’s internal transconductance amplifier to start sourcing current, turning on U2’s internal npn transistor. This causes the collector to sink just enough current to pull down on the MOSFET gate voltage and regulate the output at 3.3 V.
R2 and C2, between U2’s Collector (COLL) and COMP pins, compensate the feedback loop for optimum transient response. Placing a sense resistor, R3, between U1’s VCC and SENSE pins allows the circuit breaker to be tripped whenever the voltage across R3 is greater than 50 mV for more than 10 µs. This corresponds to a load current of 10 A (50 mV/0.005 Ω). When the circuit breaker trips, the gate pin is immediately pulled to ground, turning off MOSFET Q1 and shutting off the 3.3-V output supply.