When I needed to create a simple tool to generate a long, event-triggered pulse,
I started with a classic one-shot and a really large capacitor. This worked
"pretty good," owing to the classic nature of the problem. There seemed
to be no enthusiasm for using a small controller to provide the one-shot function,
though. Nonetheless, there may be several advantages to doing so.
Generally, larger caps have a wide initial tolerance and variation over temperature,
but a controller-based application can take advantage of Microchip’s 10F204—in
an SOT-23 package—as well as a smaller NPO capacitor, with its nearly
flat temperature variation and a 1% resistor to set the delay. This saves the
expense and footprint of larger, more expensive caps that otherwise may be needed.
This implementation codes the 10F204 with a delay translator that takes a
calculated delay, determined by the small RC components, and generates a proportionally
long output pulse. The external RC values in the circuit in Figure
1 depend on how many basic, 5-µs steps are required to trip the 10F204’s
on-chip comparator, when it’s referred to its internal 0.6-V reference.
Sequenced processes maintain the external capacitor in a discharged state and
float the input, monitoring the comparator output to determine the time to charge
above the reference. These external components are evaluated at power-up, when
the controller is re-enabled and during the first 1-ms timing step following
each trigger.
The remaining coded processes provide the enable, retrigger qualification,
multiplier, and loop indexing within a branch-equalized 1-ms loop.
Equation 1 calculates the values of R and C needed to create the desired delay
described in Equations 2 and 3.
Loops = ABS(INT(R*C* (ln(1-VTRIP/VCHARGING))/5 µs))
(1)
VTRIP is the reference comparator voltage. VCHARGING
is the voltage source used to charge the external capacitor and should be a
stable value greater than VTRIP. In this example, it’s the
same as the regulated VDD used to power the controller.
Several operational parameters are needed to define this code-based application.
These include:
1. Selection of low-to-high and high-to-low trigger edge sense:
- 0 configures the TMR0 clock input edge for low-to-high trigger
- 1 configures the TMR0 clock input edge for high-to-low trigger
2. Selection of either single-trigger or retrigger operation:
- 0 configures for single-trigger operation (triggers during active and output
are ignored),
- 1 configures for retrigger operation (any trigger reinitializes the delay).
3. Defining the 8-bit loop multiplier used in the delay computation (see below).
4. An internal state flag, capsen, configured to determine how the detected
component-based loop count is processed:
- state flag = 0 uses the calculated Loop count value directly and is constrained
to a value of 1 to 127
- state flag = 1 subtracts the calculated Loop value from 256, resulting
in a value of 255 to 128