Cutting-Edge Breakthroughs Expand ADC Boundaries

Analog-to-digital converters (ADCs)—the workhorses of the industry—have plowed their way through applications like industrial process control, medical instrumentation, communication systems, and radar for decades. Continual increases in performance specs have kept these blue-collar devices in step with the latest advances.

February's International Solid State Circuits Conference (ISSCC) in San Francisco presented the cream of the ADC crop. A number of papers on the Nyquist Track redefined the state of the art, while two pushed into new territory. And, let's not forget the latest announcements from the usual suspects.

ICY ADCs
"A Cryogenic ADC Operating Down to 4.2K" from IMEC and KU Leuven describes a successive approximation register (SAR) ADC for applications down to 4.2 Kelvin, a temperature where transistors work differently from what most of us are used to. The chip is an 8-bit SAR implemented in a conventional 0.7-mm CMOS technology. Its sampling rate is 3 kHz. At 5 V, it consumes 350 mW for a 300-pF load capacitance.

"Low-temperature detectors for X-ray and far-IR imaging and spectroscopy for space exploration and particle experiments require proximity electronics also cooled to deep cryogenic temperatures," the paper says. "Cryogenic ADCs would improve signal integrity between cold and warm electronics."

The problem with operating at cryogenic temperatures is a phenomenon called "carrier freeze." Below 77 K, a level where CMOS performs better than at normal temperatures, problems include hysteretic irregularities in the I-V transfer characteristic, including a negative transconductance region (Fig. 1).

The authors used quasi-empirical design methods to create a CMOS ADC functional between ambient temperature and 4.2 K. They simulated its low-temperature characteristics with Spice, using parameters extracted from cryogenic transistor measurements. Their chip comprises "a capacitive DAC (digital-to-analog converter), a charge-transfer preamplifier (CTA), a latched comparator, and an externally set-table SAR" (Fig. 2).

According to the authors, "While cooling the ADC from ambient temperature down to 4.2 K, no instabilities or hysteresis induced by the low temperature are observed. The INL (integral nonlinearity) increases from 0.5 to 20.8 LSB (least significant bit) and the DNL (differential nonlinearity) from 0.4 to 1.1 LSB."

In "A 50GS/s Distributed T/H Amplifier in 0.18 mm SiGe BiCMOS," authors from Alcatel-Lucent present a 50Gsample/s distributed track-and-hold amplifier (DTHA) based on a distributed topology. Addressing the pressure for increased sampling rates in high-bit-rate optical transceivers and millimeter-wave radios, they created the three-stage DTHA using distributed microstrip lines to enhance bandwidth. The amplifier exhibits a spurious-free dynamic range (SFDR) better than 40 dB.

"The DTHA has a lumped input buffer consisting of an emitter-degenerated differential amplifier preceded by a pair of emitter followers. The input has 50-V on-chip resistors to provide a good input match. The input buffer provides unity gain and very low output impedance to drive the distributed switched emitter followers and output buffer (SEFOB) stages," the paper says.

"To avoid multiple reflections between the input buffer output and the termination of the distributed SEFOB input line, the differential amplifier has load resistors of 50 V, which approximately match the image impedance of the distributed SEFOB stage. Active current sources are used for all building blocks to enhance the CMRR (common-mode rejection ratio) at low frequencies and provide a more flexible way to modulate the current," it notes.

"The distributed SEFOB stages consist of three identical SEFs and output buffers connected by balanced microstrip transmission lines," the paper continues. "The clock distribution is the most important factor to account for sampling jitter... [A] cascode architecture is used to decrease the capacitive loading of the output and to minimize the bandwidth degradation caused by Miller capacitance... The distributed output stage generates the sequence of ‘Track' and ‘Hold' control signals for the SEFOB cells."

DELTA-SIGMA SURPRISES
During ISSCC's delta-sigma track, ADC designers revealed advances in dynamic range and power consumption. For example, "A 56mW CT Quadrature Cascaded SD Modulator with 77dB DR (dynamic range) in a Near Zero-IF 20MHz Band" from NXP/Philips describes a cascaded delta-sigma modulator with continuous-time (CT) quadrature loop filters (Fig. 3).

"The first stage consists of the quadrature loop filter QLF1, A/D converters ADC1i and ADC1q, and feedback D/A converters DAC1i and DAC1q. The quantization error, Qi+jQq, of the first stage is obtained by feeding digital outputs Y1i and Y1q to D/A converters DAC2i and DAC2q, respectively, and subtracting their outputs from the inputs of ADC1i and ADC1q," the paper says.

"This quantization error signal, Qi+jQq, is then fed to a second cascaded stage comprising loop filter QLF2, A/D converters ADC2i and ADC2q, and D/A converters DAC3i and DAC3q. The digital outputs of the two stages both contain the quantization error Qi+jQq, but with different transfer functions. Therefore, the second stage output is fed to a digital quadrature noise-cancellation filter (QNCF) in order to match both transfer functions.

"Subtraction of the QNCF output from a delayed version of the first stage digital output cancels out Qi+jQq. The resulting signal Yi+jYq has very little quantization noise in the band of interest. Finally, a quadrature decimation filter (QDF) filters off the out-of-band quantization noise," the paper concludes.

Turning to other architectures, "A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS" proposes that subranging ADCs are ideal for mixed-signal ASICs. Written by Huber, et al., at UCLA, it describes a 10-bit, 160-Msample/s sub-ranger (5-bit coarse ADC, 6-bit fine ADC, with associated preamps and comparators) with an integral THA.

The prototype consumes 84 mW at 1 V and achieves better than 9.1 equivalent number or bits (ENOB) and 75-dB spurious-free dynamic range (SFDR) across the full Nyquist band, retaining 8.5 ENOB and 7-dB SFDR to 200 MHz. In the design, the coarse ADC and fine ADC sampling switches are clocked on opposite clock phases, which increases fine ADC latency by 1/2 clock period. This gives the coarse ADC time to perform its quantization.