EDA Alert: January 6, 2003

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
January 6, 2003

=============================

*************************ADVERTISEMENT***********************************
True Circuits introduces new line of low-jitter Spread Spectrum
and Low Bandwidth PLLs

True Circuits, Inc. now offers a Low Bandwidth PLL that multiplies an input clock
by a fixed-point number (1-16) and a Spread Spectrum PLL that multiplies by 92-184.
Both support wide frequency ranges and are available in 0.25um through the leading-edge
logic processes of TSMC and UMC. For information on these and other PLL designs,
call (650) 691-2500 or visit:
www.truecircuits.com/ed1
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EG0Ah
*************************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

Please see below for unsubscribe and address-change instructions.

Today's Table of Contents:
1. Axis Rolls Entry-Level Verification Systems
2. Summit Advances SystemC Verification
3. Future Design Hosts Behavioral Synthesis Workshops
4. Worldwide IC Sales Continue Growth
5. Analog Design Automation Notches First Tapeout
6. Happenings
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
DATE 03

************
1. News
************
Axis Rolls Entry-Level Verification Systems
Entry-level versions of Axis Systems' Xcite and Xtreme verification systems are
now available to design teams working on SoCs for portable systems. Both systems
feature four ReConfigurable Computing (RCC) processor boards and new software
to increase overall performance.

Both the Xcite 2500 simulation accelerator and Xtreme, combining simulation and
emulation in a single box, support assertion and behavioral processors, as well
as RTL and gate processors. Axis has added extended memory options for Xcite not
available in previous versions.

Both four-board systems are available now. Based on configuration, the Xcite system
starts at $0.09/ gate and the Xtreme system begins at $0.11/ gate.
www.axiscorp.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK0paN0AF

*******
2. News
*******
Summit Advances SystemC Verification
Release 3.1 of Summit Design's Visual Elite SystemC verification platform enables
designers to use SystemC for hardware modeling while providing ultra fast simulation,
with a direct mapping into HDL for synthesis. Release 3.1 includes FastC constructs
for HW modeling, including bi-directional ports, tri-state resolved values, an
advanced wait-statements set for testbench modeling, and comprehensive debugging
features for mixed FastC/HDL design. Visual Elite with FastC is a high performance
verification platform with modeling capabilities similar to HDL that now provides a
bridge between competing approaches to SystemC design.

Visual Elite 3.1 is available now, with prices beginning at $15,000 U.S.
www.sd.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EO0Ap

*******
3. News
*******
Future Design Hosts Behavioral Synthesis Workshops
Future Design Automation invites algorithm developers, system architects, hardware
designers and verification engineers to attend its behavioral synthesis workshop
and learn how to create synthesizable RTL from C-algorithm descriptions.

The workshops will take place at:
Future Design Automation
675 N. First Street, Suite PH3
San Jose, CA 95112

Workshops will be held:
Friday, January 10, 1:30-5:30
Friday, January 17, 1:30-5:30
Friday, January 24, 1:30-5:30

To register, e-mail rich@future-da.com with the words "Training Class" in the
subject line and the date you would like to attend.
For more information, please call (408) 279-3135.

*******
4. News
*******
Worldwide IC Sales Continue Growth
According to the Semiconductor Industry Association, global semiconductor sales
reached $12.68 billion in November 2002, a 1.3% sequential increase from the
$12.51 billion in revenue reported in October 2002 continuing the trend that
began in the fourth quarter 2001. November sales are up 19.6% from November 2001
sales of $10.60 billion.

"The November sales of the global chip industry underscores the healthy recovery
that has been building momentum through out this year," stated SIA President
George Scalise. "The wireless sector continues to be the strongest single market."

The semiconductor products that benefit from the strength of the wireless sector
are led by Flash and digital dignal processors, which were up 6.6% and 3.7% in
November. In addition, Wi-Fi has begun to contribute to the strength of this
market. Furthermore, the computer segment continues to show growth with
microprocessors up 0.5% and DRAM's increasing by 5.8%.

Chip sales rose 5.8% in November in the European market and 1.3% in Asia
Pacific. Semiconductor sales in the Americas declined slightly by 0.8%
and 0.6% in Japan.
www.sia-online.org
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EI0Aj

*******
5. News
*******
Analog Design Automation Notches First Tapeout
ControlNet, Inc., a developer of chip cores, circuit designs, and software for the
LAN/WAN and FireWire markets, has successfully taped out its first FireWire
design using Analog Design Automation's (ADA's) Genius product line. Genius
allowed ControlNet to analyze and optimize three analog design blocks in only
three weeks, including testbench time. "ControlNet's chip is ADA Genius' first
publicly announced design to reach tapeout," said Matthew Raggett, president
and CEO of ADA.

ADA's Genius family of products includes Creative Genius, a high-capacity
optimizer, which automates component sizing and biasing to achieve optimal
circuit performance; and IP Explorer, a performance tradeoff explorer, which
allows designers to visually understand and weigh design tradeoffs.

ControlNet was having difficulty with the bandgap reference and data receiver
in its three-port 1394 PHY when it sought out ADA. The bandgap reference was
unable to meet required gain, temperature coefficient, and output voltage
requirements; and the data receiver was unable to switch over all 256 variations
at the desired frequency and input signal amplitude. As a result of using the
Genius family, ControlNet was able to optimize the two problem blocks.
www.analogsynthesis.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EJ0Ak

*************
6. Happenings
*************

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
www.designcon.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05cn0Ao

Design and Verification Conference and Exhibition (DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
www.dvcon.org
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05co0Ap

DATE 03
ICM, Munich, Germany
March 3-7, 2003
www.date-conference.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK0paO0AG

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05cp0Aq

===============================
Copyright 2003 Penton Media Inc.

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
January 6, 2003

=============================

*************************ADVERTISEMENT***********************************
True Circuits introduces new line of low-jitter Spread Spectrum
and Low Bandwidth PLLs

True Circuits, Inc. now offers a Low Bandwidth PLL that multiplies an input clock
by a fixed-point number (1-16) and a Spread Spectrum PLL that multiplies by 92-184.
Both support wide frequency ranges and are available in 0.25um through the leading-edge
logic processes of TSMC and UMC. For information on these and other PLL designs,
call (650) 691-2500 or visit:
www.truecircuits.com/ed1
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EG0Ah
*************************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design Magazine.

Please see below for unsubscribe and address-change instructions.

Today's Table of Contents:
1. Axis Rolls Entry-Level Verification Systems
2. Summit Advances SystemC Verification
3. Future Design Hosts Behavioral Synthesis Workshops
4. Worldwide IC Sales Continue Growth
5. Analog Design Automation Notches First Tapeout
6. Happenings
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
DATE 03

************
1. News
************
Axis Rolls Entry-Level Verification Systems
Entry-level versions of Axis Systems' Xcite and Xtreme verification systems are
now available to design teams working on SoCs for portable systems. Both systems
feature four ReConfigurable Computing (RCC) processor boards and new software
to increase overall performance.

Both the Xcite 2500 simulation accelerator and Xtreme, combining simulation and
emulation in a single box, support assertion and behavioral processors, as well
as RTL and gate processors. Axis has added extended memory options for Xcite not
available in previous versions.

Both four-board systems are available now. Based on configuration, the Xcite system
starts at $0.09/ gate and the Xtreme system begins at $0.11/ gate.
www.axiscorp.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK0paN0AF

*******
2. News
*******
Summit Advances SystemC Verification
Release 3.1 of Summit Design's Visual Elite SystemC verification platform enables
designers to use SystemC for hardware modeling while providing ultra fast simulation,
with a direct mapping into HDL for synthesis. Release 3.1 includes FastC constructs
for HW modeling, including bi-directional ports, tri-state resolved values, an
advanced wait-statements set for testbench modeling, and comprehensive debugging
features for mixed FastC/HDL design. Visual Elite with FastC is a high performance
verification platform with modeling capabilities similar to HDL that now provides a
bridge between competing approaches to SystemC design.

Visual Elite 3.1 is available now, with prices beginning at $15,000 U.S.
www.sd.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EO0Ap

*******
3. News
*******
Future Design Hosts Behavioral Synthesis Workshops
Future Design Automation invites algorithm developers, system architects, hardware
designers and verification engineers to attend its behavioral synthesis workshop
and learn how to create synthesizable RTL from C-algorithm descriptions.

The workshops will take place at:
Future Design Automation
675 N. First Street, Suite PH3
San Jose, CA 95112

Workshops will be held:
Friday, January 10, 1:30-5:30
Friday, January 17, 1:30-5:30
Friday, January 24, 1:30-5:30

To register, e-mail rich@future-da.com with the words "Training Class" in the
subject line and the date you would like to attend.
For more information, please call (408) 279-3135.

*******
4. News
*******
Worldwide IC Sales Continue Growth
According to the Semiconductor Industry Association, global semiconductor sales
reached $12.68 billion in November 2002, a 1.3% sequential increase from the
$12.51 billion in revenue reported in October 2002 continuing the trend that
began in the fourth quarter 2001. November sales are up 19.6% from November 2001
sales of $10.60 billion.

"The November sales of the global chip industry underscores the healthy recovery
that has been building momentum through out this year," stated SIA President
George Scalise. "The wireless sector continues to be the strongest single market."

The semiconductor products that benefit from the strength of the wireless sector
are led by Flash and digital dignal processors, which were up 6.6% and 3.7% in
November. In addition, Wi-Fi has begun to contribute to the strength of this
market. Furthermore, the computer segment continues to show growth with
microprocessors up 0.5% and DRAM's increasing by 5.8%.

Chip sales rose 5.8% in November in the European market and 1.3% in Asia
Pacific. Semiconductor sales in the Americas declined slightly by 0.8%
and 0.6% in Japan.
www.sia-online.org
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EI0Aj

*******
5. News
*******
Analog Design Automation Notches First Tapeout
ControlNet, Inc., a developer of chip cores, circuit designs, and software for the
LAN/WAN and FireWire markets, has successfully taped out its first FireWire
design using Analog Design Automation's (ADA's) Genius product line. Genius
allowed ControlNet to analyze and optimize three analog design blocks in only
three weeks, including testbench time. "ControlNet's chip is ADA Genius' first
publicly announced design to reach tapeout," said Matthew Raggett, president
and CEO of ADA.

ADA's Genius family of products includes Creative Genius, a high-capacity
optimizer, which automates component sizing and biasing to achieve optimal
circuit performance; and IP Explorer, a performance tradeoff explorer, which
allows designers to visually understand and weigh design tradeoffs.

ControlNet was having difficulty with the bandgap reference and data receiver
in its three-port 1394 PHY when it sought out ADA. The bandgap reference was
unable to meet required gain, temperature coefficient, and output voltage
requirements; and the data receiver was unable to switch over all 256 variations
at the desired frequency and input signal amplitude. As a result of using the
Genius family, ControlNet was able to optimize the two problem blocks.
www.analogsynthesis.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK07EJ0Ak

*************
6. Happenings
*************

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
www.designcon.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05cn0Ao

Design and Verification Conference and Exhibition (DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
www.dvcon.org
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05co0Ap

DATE 03
ICM, Munich, Germany
March 3-7, 2003
www.date-conference.com
click here => http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK0paO0AG

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
PlanetEE's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eO6V0DJhFR0BSK05cp0Aq

===============================
Copyright 2003 Penton Media Inc.