EDA Alert: June 7, 2005

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EDA Alert e-Newsletter
PlanetEE - www.planetee.com
Electronic Design - www.elecdesign.com
June 7, 2005

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Today's Table of Contents:
1. Viewpoint Exclusive -- EDA's Own Mine Shaft Gap
2. Integration Links Verification Platform With Debug Tools
3. Mixed-Signal Process Design Kits Cut Development Cost
4. New SCE-MI Standard Gets Approval
5. Hierarchy Comes To Timing Closure
6. Happenings
- Annual Conference of American Society for Engineering
Education (ASEE 2005)
- Design Automation Conference (DAC)
- Management Day at DAC
- 2005 Symposia on VLSI Technology and Circuits

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See Synopsys at DAC 2005! June 13-17 in Anaheim, CA

Synopsys brings the industry's most innovative products to market,
including IC Compiler, our next-generation physical design system;
PrimeRail for power network signoff; and VCS(R) for comprehensive
verification in Booth 1088; see our complete analog/ mixed-signal
solution in Booth 700.

Register Now!

http://nls.planetee.com/t?ctl=B8FF:F3222

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TAKE A POLL: Do you think RFID applications such as smart cards,
passports, and drivers' licenses are an invasion of privacy?

-- No, it's a great boost to security
-- Yes, but it's a necessary evil
-- Yes, we should preserve privacy rights
-- Don't know

Electronic Design's Quick Poll ==> http://nls.planetee.com/t?ctl=B908:F3222
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Free Webcast: What to See at DAC
Friday, June 10 at 11 am PT/2 pm ET

It's a highly coveted honor to be on the "What to See at DAC" list
compiled for each year's Design Automation Conference by Gartner
Dataquest's Gary Smith. Those EDA tool vendors who make the cut have
been singled out by the EDA industry's leading analyst as having one
of 2005's hottest EDA tools or technologies. This year's "What to
See at DAC" list will make its debut in Electronic Design's DAC ShowCast
when Smith, along with EDA Technology Editor David Maliniak, will offer
a preview of the best of this year's DAC. Take a virtual tour of the
show floor and get an advance glimpse of EDA's premier technology
showcase.

Register today at:
http://nls.planetee.com/t?ctl=B900:F3222

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Get The Lead Out!

The European Union, as well as Japan and China, are about to
restrict the use of environmentally hazardous materials in
electronic components and systems through the Restrictions on
Hazardous Substances (RoHS) directive. Check out Electronic Design's
new RoHS Reference Center with links, articles, and more. Take our
RoHS quiz to see how much you really know about this new EU
directive. Then download the first chapter of our eBook, "Electronic
Design's Guide To New International Environmental Laws." And stay
tuned for more chapters to learn everything you need to know about
this important emerging topic.

RoHS e-book ==> http://nls.planetee.com/t?ctl=B909:F3222

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SUBSCRIBE ONLINE TO ELECTRONIC DESIGN
If you're reading this e-newsletter, then you are either a current
Electronic Design subscriber, or should be (145,000 of your peers
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Electronic Design subscription ==>
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1. Viewpoint -- Exclusive to EDA Alert
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EDA's Own Mine Shaft Gap

Adam Traidman, President and VP of Business Development
Giga Scale IC, Cupertino, Calif.

There's a brilliant comic moment in Stanley Kubrick's classic 1964
film, "Dr. Strangelove," in which U.S. military and political
leaders, facing imminent nuclear holocaust, begin discussing the
possibility of a "mine shaft gap." The notion holds that government
officials will take shelter in deep, heavily stocked mine shafts
before the bombs fall, with their progeny emerging some 100 years
after the irradiated earth cools down. The fear is that if more
survivors emerge from the Soviet mine shaft than from the American
one, they will take over what is left of the world.

Similarly, there is a growing gap in IC design, not as darkly
comical but nearly as deep as a mine shaft. This rift started to
open as chip designers began demanding tools that enabled them to
produce architectural definitions at increasingly higher levels of
abstraction. The EDA industry dutifully responded with technologies
such as electronic-system-level (ESL) methodologies, resulting in a
platform for rapid architectural definition and faster design
verification. For design team members, one unintentional but perhaps
inevitable consequence of using these new technologies was a
pronounced dissociation between the increasingly high-level design
architecture and the final physical chip implementation.

The recent explosion in IP and manufacturing options available at
130 nm and 90 nm has fueled the widening of this design gap. As
designers move up to increasingly higher levels of abstraction, and
as the physical implementation landscape grows more complex, design
teams have less and less insight into the technical and
(particularly) the economic ramifications of physical chip
implementation. And, unfortunately, these technical and financial
implications often dictate the success or failure of the final IC
product.

A new breed of EDA tools designed to perform architectural analysis
and exploration could help significantly reduce the design gap.
These tools would provide design teams with a foundation for
technology exploration, allowing them to optimize design
specifications and map high-level models to a physical
implementation. The ability to execute accurate and rapid "what-if"
analysis coupled with exploration of various implementation options
would provide an understanding of how best to balance many mutually
exclusive design goals, such as size, power consumption, leakage,
yield, and cost. With proper physical mapping, the design
architecture could then be estimated, and the resulting design goals
(as noted above) could be accurately derived. Such tools would
enable design teams to make key decisions early in the design flow
when they matter most, and facilitate the creation of a
specification that meets functional as well as economic
requirements.

The world leaders in "Dr. Strangelove" were so disconnected from
their immediate problems (i.e., impending nuclear doom) that they
focused on absurd ones such as mine shaft gaps. IC design teams,
often insulated from the economic impact of their design decisions,
may face an identical fate unless they pick up a new set of tools to
harness the power of designing for cost. Cost has become such an
immediate problem in the domain of IC design that it is evolving
from a business issue to an engineering problem.

Contact Adam Traidman at: mailto:adam@gigaic.com

To comment on this Viewpoint, go to Reader Comments at the foot of
the Web page:
EDA Alert ==> http://nls.planetee.com/t?ctl=B902:F3222

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2. News
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Integration Links Verification Platform With Debug Tools

A collaborative effort by Emulation and Verification Engineering
(EVE) and Novas Software brings interoperability between EVE's
hardware-assisted verification platform and Novas' Verdi automated
debug system. The result is a single, unified interface for the
development, verification, and debug of SoC designs and an optimized
verification flow between EVE's ZeBu (Zero Bugs) platform and Verdi.

With verification and debug still the most time-consuming portions
of SoC design projects, the integration effort gives designers a
means of quickly tracking and correcting the causes of design bugs
before fabricating silicon. Additional integration efforts between
the two companies will be announced later in 2005.

EVE ==> http://nls.planetee.com/t?ctl=B90D:F3222
Novas Software ==> http://nls.planetee.com/t?ctl=B90F:F3222

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3. News
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Mixed-Signal Process Design Kits Cut Development Cost

An agreement between X-FAB Semiconductor Foundries AG and Tanner EDA
has culminated in comprehensive design kits for analog/mixed-signal
ICs targeting mainstream process technologies. The collaboration
ensures that design teams can accelerate product development and
achieve high levels of design quality while keeping EDA costs
tightly under control.

In addition to the existing Tanner PDKs (Process Development Kits)
at the 1-, 0.8-, 0.6-, and 0.35-micron process nodes, X-FAB released
its latest Tanner PDK Design Kit for the 0.35-micron, 3.3-V biCMOS
process this past April. The 0.35-micron biCMOS technology offers
three- or four-layer metallization with the option for an
alternative thick fourth-layer metallization, double poly and MiM
capacitor as well as high-resistive poly. This technology is
especially suited for RF circuits and high-precision analog
applications.

Tanner EDA ==> http://nls.planetee.com/t?ctl=B90E:F3222

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4. News
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New SCE-MI Standard Gets Approval

Accellera's board of directors approved version 1.1 of the Standard
Co-Emulation Modeling Interface (SCE-MI) standard. The SCE-MI
specification improves high-speed, transaction-level verification
between different hardware and software simulation and emulation
systems. SCE-MI 1.1 improves model portability between different
verification acceleration tools.

In the past, transaction-level modeling (TLM) lacked proper support
from accelerated verification systems. SCE-MI allows transactor
models to run on the accelerator rather than in the software
simulator, which speeds up the models and communications with the
accelerator.

Accellera's Interface Technical Committee is already at work
defining the next version of the SCE-MI specification, which will
make it simpler and enable use of SCE-MI transactors for simulation
and acceleration. A plan for that next version is to be completed by
year's end.

Accellera ==> http://nls.planetee.com/t?ctl=B907:F3222

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5. News
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Hierarchy Comes To Timing Closure

With more IC designs being approached hierarchically, design teams
pay a price when tools can't optimize across physical hierarchical
boundaries. Manhattan Routing's timing-closure tool enables design
teams to analyze and optimize such designs without having to create
the often inefficient and inaccurate models used to merge multiple
levels of physical hierarchy.

The Hierarchical Physical Window/Optimization Cockpit (hPW/hOC)
eliminates inefficiencies created by the physical partitioning of
ASICs and allows a seamless view of the nets and paths that cross
the physical boundaries. The tool operates from a very fast database
and uses the actual physical, logical, and timing information from
the various levels of physical hierarchy for the analysis and final
optimization of chips.

Pricing for a three-year, time-based license starts at $36,000 for
analysis capabilities and $84,000 for optimization capabilities. The
analysis features of hPW/hOC are available now; the optimization
features will be available in the fourth quarter.

Manhattan Routing ==> http://nls.planetee.com/t?ctl=B90A:F3222

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6. Happenings
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Annual Conference of American Society for Engineering Education
(ASEE 2005)
Oregon Convention Center, Portland, Ore.
June 12-15, 2005
http://nls.planetee.com/t?ctl=B901:F3222

Design Automation Conference (DAC)
Anaheim Convention Center, Anaheim, Calif.
June 13-17, 2005
http://nls.planetee.com/t?ctl=B910:F3222

Management Day at DAC
Anaheim Convention Center, Anaheim, Calif.
June 14, 2005, 8:00 a.m. to 5:00 p.m.
Hear first-hand how managers from companies like Cisco, eSilicon,
Freescale, Intel, Philips, and PMC-Sierra
made crucial design-business decisions. The day includes the EDA
Business Forum Luncheon and an exclusive cocktail party.
http://nls.planetee.com/t?ctl=B904:F3222

2005 Symposia on VLSI Technology and Circuits
Rihga Royal Hotel Kyoto, Kyoto, Japan
June 14-18, 2005
http://nls.planetee.com/t?ctl=B90B:F3222

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Take the Infineon Memory Challenge

We have an all new pop-quiz for you to test your memory skills on!
Take a whack at the five memory-related questions and you could win
a super-duper Sony Playstation Portable device. We'll also be
throwing a few Electronic Design T-shirts into this month's quiz, so
put your knowledge to the test and hit that submit button!

http://nls.planetee.com/t?ctl=B903:F3222
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A Closer Look At Video Signals

Nowadays there are numerous standards for the digital video signals
widely used in such products as game players and cell phones. Tough
design questions arise, however, because those digital signals must
be dealt with in an analog domain. Get the answers in a new eBook,
"Analog/Mixed-Signal Components For 21st Century Video," by
Analog/Power Editor Don Tuite.

http://nls.planetee.com/t?ctl=B905:F3222
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EDA ALERT e-NEWSLETTER CONTACTS

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EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities: Bill Baumann
mailto:bbaumann@penton.com

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