EDA Alert: November 19, 2002

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
November 19, 2002

=============================

*************************ADVERTISEMENT***************************
FREE technical presentation
Co-Verification for Configurable SoC Platforms
Learn to:
~ Improve product quality by fine-tuning the hardware/software
interface before tape-out
~ Develop an ASIC with a configurable processor
~ Boost system performance using the ARCtangent(tm) and
Seamless(r)
Register today!
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K50As
*****************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design
Magazine.
Please see below for unsubscribe and address-change instructions.


Today's Table of Contents:
1. Viewpoint Exclusive - COT or ASIC? That's Not The Choice!
2. LSI Logic Rolls Out RTL Optimization
3. 0-In Expands Its Monitor Offering
4. Support Grows For e Verification Language
5. AWR Licenses Synopsys HSPICE For RFICs
6. Virtual Silicon Readies IP For IBM's 130-nm Process
7. Happenings
Conference on Design of Circuits and Integrated Systems (DCIS)
SynTest Seminar On SoC Test Cost Reduction
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)

************
1. Viewpoint - Exclusive to EDA Alert
************
COT or ASIC? That's Not The Choice!
Bob Dahlberg, Vice President Of Marketing
ReShape Inc., Mountain View, CA

Twenty years ago LSI Logic presented a choice to consumers of
custom silicon at mainframe and mini-computer manufacturers: You
can use your captive tools to design custom chips to be
manufactured in your captive fab, to be packaged by your captive
packaging group, and tested by captive test, or you can go the ASIC
("custom") route to a one-stop shop that specializes in
semi-custom chips and at one-third to one-fifth the total cost.
Four years later, captive fabs at system houses died.

Today's trend toward customer-owned tooling (COT) is bringing an
end to the ASIC chapter; customers now have direct access to
best-in-class "links in the supply chain." Everything you need to
build a complex IC is available freely in the marketplace. Tools
come from the competitive EDA industry. There is plenty of silicon
intellectual property (IP), and some of it is"free." Quality silicon
foundries exist in Asia Pacific or New York; an abundance of
assembly and test capacity exists in Malaysia.

Almost every day an ASIC supplier customer knocks on our door
asking us to facilitate their move to the COT world. They're
being driven toward COT by schedules and costs. Although they're
happy with ASIC's near-zero non-recurring engineering (NRE)
charges, they are unhappy with the unpredictability of the amount
of time it takes their ASIC supplier to convert a netlist into
GDSII for mask making. They are also unhappy with high
piece-part prices.

But customers are also concerned about taking on the complexities
and cost of buying expensive physical design tools and hiring
physical design gurus to use them. They know this is hard because
of the long project delays from their suppliers and that the big
tool suppliers are out selling "methodology consulting." They
worry about the variable quality of silicon IP. Their heads are
spinning from managing a foundry and assembly and test. In the
end, what holds them back is the COT model, in which no single
link in the chain can be held responsible for working silicon.
Only the customer holds that responsibility; and those who don't
want that responsibility retreat to the devil they know: their
ASIC supplier.

Savvy ASIC suppliers know that customers want working chips at a
reasonable price. They have assessed their own core competencies,
and they have answered the questions: Can they develop better
process technology? Can they develop higher quality silicon IP?
Can they provide better physical design? Better test? Better
assembly? Better throughput? When these savvy suppliers find
that the answer is no, they seek best-in-class suppliers to fill
the hole. At ReShape, we've shepherded both ASIC suppliers and
system houses through the process of achievingpredictable SoC
tapeouts.

The ultimate competitive advantage for the ASIC industry is
accepting project risk across all elements in the semiconductor
value chain. For that they will get a piece-part premium.
Customers who accept the risk will build and manage their own IC
supplier value chain and go COT. Ultimately, from underneath,
the two approaches will look very similar: The actual work
beyond creating an RTL netlist will be done by outsourced
suppliers. The difference will be who--a single vendor or the
customer themselves--takes responsibility for delivering fully
functional chips that work at speed and at reasonable cost.

Send comments directly to the author at: bobd@reshape.com
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LU0AR

*******
2. News
*******
LSI Logic Rolls Out RTL Optimization
Identifying physical design issues early is a key to success in
complex SoC design cycles. LSI Logic's Physical RTL Optimization
(PRO) design flow directly links routing and congestion problems
in physical design back to the RTL code, while the code is still
being developed, allowing engineers to quickly and predictably
resolve major physical design issues at the RTL stage. The flow
minimizes the number of iterations between logical and physical
design, allowing engineers to achieve predictable design
closure.

In complex SoC designs, major physical design issues must be
resolved in either the chip-level architecture or the RTL
architecture and coding. Once RTL is coded, resolving major
physical design issues often requires time-consuming iterations.
The LSI Logic PRO flow provides a pre-emptive diagnosis on the
RTL code, allowing early visibility into issues such as routing
congestion and critical-path timing violations created by
sub-optimal RTL coding and architecture.

The PRO design flow centers on Tera Systems Inc.'s TeraForm LPA
(LSI ProAnalyzer) physical RTL analysis tool. Built on Tera
Systems' RTL Silicon Virtual Prototype (SVP) technology, TeraForm
LPA combines LSI Logic's PRO Rule Checker with the LSI PRO
Physical RTL Rule Set. The LSI PRO Physical RTL Rule Set
encapsulates the collective experience and expert knowledge of
LSI Logic's ASIC design centers.

LSI Logic targets physical RTL optimization on all of its Gflx
0.11-micron and G90 90-nm designs, as well as the majority of its
G12 0.18-micron designs. TeraForm LPA, containing a diverse
starter set of LSI Logic semantics, structural and implementation
rules with an optimized and scalable TeraGate library is
available immediately from Tera Systems at a price of $25,000 US
list per year for a time-based license.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K60At
and http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K70Au

*******
3. News
*******
0-In Expands Its Monitor Offering
CheckerWare monitors are now available from 0-In for the AGP 8x,
HyperTransport, InfiniBand and RapidIO standards. IC design teams
and assertion-based verification (ABV) users can increase
verification productivity by using these pre-verified Verilog RTL
monitors to validate compliance with the latest protocol and
interface standards.

CheckerWare monitors offer formal tool support, testbench and
simulator independence, and interoperability with all tools in
existing verification environments. They certify that the designs
conform to interface standards and enable products to be
interoperable with all products that support these standards.
During simulation, CheckerWare monitors warn users of any
protocol violations and generate structural coverage statistics
to measure testbench efficacy. The same monitors serve as targets
and constraints to guide formal verification tools, including the
0-In Search dynamic formal verification tool.

The AGP 8x, HyperTransport, InfiniBand and RapidIO monitors are
the latest interface models to emerge from the 0-In development
pipeline; PCI Express and Serial-Attached SCSI monitors are among
the next group of models also to be delivered this quarter.

Visit http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K80Av
to contribute to an ongoing interface and protocol standards survey
and become eligible for prizes.

*******
4. News
*******
Support Grows For e Verification Language
ARM, Infineon Technologies, LSI Logic Corp. and PMC-Sierra have
all joined the LicenseE program in an effort to drive Verisity's
e verification language toward public standardization. LicenseE
partners automatically become part of the e language Steering
Committee, whose purpose is to drive the e language to
standardization to better serve the verification market. All
companies on the Steering Committee have equal say, including
Verisity.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK0paJ0AZ

*******
5. News
*******

AWR Licenses Synopsys HSPICE For RFICs
Applied Wave Research Inc. (AWR) has reached a technology
licensing agreement with Synopsys that enables AWR to integrate
Synopsys' HSPICE analog and mixed-signal circuit simulation
technology into its high-frequency design environment. This
agreement will provide radio frequency integrated circuit (RFIC)
designers with the ability to improve simulation performance
and reduce development time in designing large-scale RFICs used
in wireless and wireline appliances.

The agreement between AWR and Synopsys enables AWR to deliver a
more advanced RFIC design flow that combines AWR's design
environment with Synopsys' HSPICE analog simulation technology.
AWR expects to deliver tools based upon the Synopsys HSPICE
technology in the first half of 2003.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LA0A6

*******
6. News
*******
Virtual Silicon Readies IP For IBM's 130-nm Process
Virtual Silicon Technology Inc. has launched a family of IP
products targeted for the IBM 130-nm foundry process. The
offering includes Virtual Silicon's basic I/O, phase-locked loop
(PLL), delay-locked loop (DLL), high-speed interface products and
standard cells.

Virtual Silicon's high-speed interface products are targeted at
providing physical layer solutions for next generation chip to
chip communications. Products include SSTL2, HSTL, LVDS, PCI 2.2
and PCI-X. The high-speed interface products are coupled with
highly accurate PLLs and DLLs to provide customers with complete
QDR (HSTL) and DDR (SSTL2) solutions. The offering includes basic
CMOS I/O's that are flip-chip and area-array compatible.

Virtual Silicon IBM product offering is available for license
now, and has already been used by three customers for the
development of SoC designs for IBM's 130-nm process. Virtual
Silicon's IP has been designed specifically for the IBM 130-nm
(8SF) foundry process. Additional products will be offered to
customers in first half of 2003.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LV0AS

*************
7. Happenings
*************

Conference on Design of Circuits and Integrated Systems (DCIS)
Palacio de la Magdalena, Sanstander, Spain
November 19-22, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05cm0AD

SynTest Seminar on SoC Test Cost Reduction
DoubleTree Hotel - Irvine Spectrum, Irvine, CA
Wednesday, November 20, 2002
9.30 a.m. to 1.00 p.m., followed by lunch
To register, please contact Marc Brodnansky at
brodnansky@syntest.com or call 310-265-1304

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05cn0AE

Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05co0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
Penton's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eNOj0DJhFR0C4C0Jvu0Ah

===============================
Copyright 2002 Penton Media Inc.

==================================

EDA Alert e-Newsletter
PlanetEE - www.planetee.com
November 19, 2002

=============================

*************************ADVERTISEMENT***************************
FREE technical presentation
Co-Verification for Configurable SoC Platforms
Learn to:
~ Improve product quality by fine-tuning the hardware/software
interface before tape-out
~ Develop an ASIC with a configurable processor
~ Boost system performance using the ARCtangent(tm) and
Seamless(r)
Register today!
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K50As
*****************************************************************

You've received this e-newsletter for one of three reasons:
1) you received our EDA Alert newsletter in the past,
2) you've signed up for it at http://www.planetee.com, or
3) you've identified yourself as a specifier of EDA tools on
your qualification form as a reader of Electronic Design
Magazine.
Please see below for unsubscribe and address-change instructions.


Today's Table of Contents:
1. Viewpoint Exclusive - COT or ASIC? That's Not The Choice!
2. LSI Logic Rolls Out RTL Optimization
3. 0-In Expands Its Monitor Offering
4. Support Grows For e Verification Language
5. AWR Licenses Synopsys HSPICE For RFICs
6. Virtual Silicon Readies IP For IBM's 130-nm Process
7. Happenings
Conference on Design of Circuits and Integrated Systems (DCIS)
SynTest Seminar On SoC Test Cost Reduction
DesignCon 2003
Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)

************
1. Viewpoint - Exclusive to EDA Alert
************
COT or ASIC? That's Not The Choice!
Bob Dahlberg, Vice President Of Marketing
ReShape Inc., Mountain View, CA

Twenty years ago LSI Logic presented a choice to consumers of
custom silicon at mainframe and mini-computer manufacturers: You
can use your captive tools to design custom chips to be
manufactured in your captive fab, to be packaged by your captive
packaging group, and tested by captive test, or you can go the ASIC
("custom") route to a one-stop shop that specializes in
semi-custom chips and at one-third to one-fifth the total cost.
Four years later, captive fabs at system houses died.

Today's trend toward customer-owned tooling (COT) is bringing an
end to the ASIC chapter; customers now have direct access to
best-in-class "links in the supply chain." Everything you need to
build a complex IC is available freely in the marketplace. Tools
come from the competitive EDA industry. There is plenty of silicon
intellectual property (IP), and some of it is"free." Quality silicon
foundries exist in Asia Pacific or New York; an abundance of
assembly and test capacity exists in Malaysia.

Almost every day an ASIC supplier customer knocks on our door
asking us to facilitate their move to the COT world. They're
being driven toward COT by schedules and costs. Although they're
happy with ASIC's near-zero non-recurring engineering (NRE)
charges, they are unhappy with the unpredictability of the amount
of time it takes their ASIC supplier to convert a netlist into
GDSII for mask making. They are also unhappy with high
piece-part prices.

But customers are also concerned about taking on the complexities
and cost of buying expensive physical design tools and hiring
physical design gurus to use them. They know this is hard because
of the long project delays from their suppliers and that the big
tool suppliers are out selling "methodology consulting." They
worry about the variable quality of silicon IP. Their heads are
spinning from managing a foundry and assembly and test. In the
end, what holds them back is the COT model, in which no single
link in the chain can be held responsible for working silicon.
Only the customer holds that responsibility; and those who don't
want that responsibility retreat to the devil they know: their
ASIC supplier.

Savvy ASIC suppliers know that customers want working chips at a
reasonable price. They have assessed their own core competencies,
and they have answered the questions: Can they develop better
process technology? Can they develop higher quality silicon IP?
Can they provide better physical design? Better test? Better
assembly? Better throughput? When these savvy suppliers find
that the answer is no, they seek best-in-class suppliers to fill
the hole. At ReShape, we've shepherded both ASIC suppliers and
system houses through the process of achievingpredictable SoC
tapeouts.

The ultimate competitive advantage for the ASIC industry is
accepting project risk across all elements in the semiconductor
value chain. For that they will get a piece-part premium.
Customers who accept the risk will build and manage their own IC
supplier value chain and go COT. Ultimately, from underneath,
the two approaches will look very similar: The actual work
beyond creating an RTL netlist will be done by outsourced
suppliers. The difference will be who--a single vendor or the
customer themselves--takes responsibility for delivering fully
functional chips that work at speed and at reasonable cost.

Send comments directly to the author at: bobd@reshape.com
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LU0AR

*******
2. News
*******
LSI Logic Rolls Out RTL Optimization
Identifying physical design issues early is a key to success in
complex SoC design cycles. LSI Logic's Physical RTL Optimization
(PRO) design flow directly links routing and congestion problems
in physical design back to the RTL code, while the code is still
being developed, allowing engineers to quickly and predictably
resolve major physical design issues at the RTL stage. The flow
minimizes the number of iterations between logical and physical
design, allowing engineers to achieve predictable design
closure.

In complex SoC designs, major physical design issues must be
resolved in either the chip-level architecture or the RTL
architecture and coding. Once RTL is coded, resolving major
physical design issues often requires time-consuming iterations.
The LSI Logic PRO flow provides a pre-emptive diagnosis on the
RTL code, allowing early visibility into issues such as routing
congestion and critical-path timing violations created by
sub-optimal RTL coding and architecture.

The PRO design flow centers on Tera Systems Inc.'s TeraForm LPA
(LSI ProAnalyzer) physical RTL analysis tool. Built on Tera
Systems' RTL Silicon Virtual Prototype (SVP) technology, TeraForm
LPA combines LSI Logic's PRO Rule Checker with the LSI PRO
Physical RTL Rule Set. The LSI PRO Physical RTL Rule Set
encapsulates the collective experience and expert knowledge of
LSI Logic's ASIC design centers.

LSI Logic targets physical RTL optimization on all of its Gflx
0.11-micron and G90 90-nm designs, as well as the majority of its
G12 0.18-micron designs. TeraForm LPA, containing a diverse
starter set of LSI Logic semantics, structural and implementation
rules with an optimized and scalable TeraGate library is
available immediately from Tera Systems at a price of $25,000 US
list per year for a time-based license.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K60At
and http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K70Au

*******
3. News
*******
0-In Expands Its Monitor Offering
CheckerWare monitors are now available from 0-In for the AGP 8x,
HyperTransport, InfiniBand and RapidIO standards. IC design teams
and assertion-based verification (ABV) users can increase
verification productivity by using these pre-verified Verilog RTL
monitors to validate compliance with the latest protocol and
interface standards.

CheckerWare monitors offer formal tool support, testbench and
simulator independence, and interoperability with all tools in
existing verification environments. They certify that the designs
conform to interface standards and enable products to be
interoperable with all products that support these standards.
During simulation, CheckerWare monitors warn users of any
protocol violations and generate structural coverage statistics
to measure testbench efficacy. The same monitors serve as targets
and constraints to guide formal verification tools, including the
0-In Search dynamic formal verification tool.

The AGP 8x, HyperTransport, InfiniBand and RapidIO monitors are
the latest interface models to emerge from the 0-In development
pipeline; PCI Express and Serial-Attached SCSI monitors are among
the next group of models also to be delivered this quarter.

Visit http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06K80Av
to contribute to an ongoing interface and protocol standards survey
and become eligible for prizes.

*******
4. News
*******
Support Grows For e Verification Language
ARM, Infineon Technologies, LSI Logic Corp. and PMC-Sierra have
all joined the LicenseE program in an effort to drive Verisity's
e verification language toward public standardization. LicenseE
partners automatically become part of the e language Steering
Committee, whose purpose is to drive the e language to
standardization to better serve the verification market. All
companies on the Steering Committee have equal say, including
Verisity.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK0paJ0AZ

*******
5. News
*******

AWR Licenses Synopsys HSPICE For RFICs
Applied Wave Research Inc. (AWR) has reached a technology
licensing agreement with Synopsys that enables AWR to integrate
Synopsys' HSPICE analog and mixed-signal circuit simulation
technology into its high-frequency design environment. This
agreement will provide radio frequency integrated circuit (RFIC)
designers with the ability to improve simulation performance
and reduce development time in designing large-scale RFICs used
in wireless and wireline appliances.

The agreement between AWR and Synopsys enables AWR to deliver a
more advanced RFIC design flow that combines AWR's design
environment with Synopsys' HSPICE analog simulation technology.
AWR expects to deliver tools based upon the Synopsys HSPICE
technology in the first half of 2003.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LA0A6

*******
6. News
*******
Virtual Silicon Readies IP For IBM's 130-nm Process
Virtual Silicon Technology Inc. has launched a family of IP
products targeted for the IBM 130-nm foundry process. The
offering includes Virtual Silicon's basic I/O, phase-locked loop
(PLL), delay-locked loop (DLL), high-speed interface products and
standard cells.

Virtual Silicon's high-speed interface products are targeted at
providing physical layer solutions for next generation chip to
chip communications. Products include SSTL2, HSTL, LVDS, PCI 2.2
and PCI-X. The high-speed interface products are coupled with
highly accurate PLLs and DLLs to provide customers with complete
QDR (HSTL) and DDR (SSTL2) solutions. The offering includes basic
CMOS I/O's that are flip-chip and area-array compatible.

Virtual Silicon IBM product offering is available for license
now, and has already been used by three customers for the
development of SoC designs for IBM's 130-nm process. Virtual
Silicon's IP has been designed specifically for the IBM 130-nm
(8SF) foundry process. Additional products will be offered to
customers in first half of 2003.
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK06LV0AS

*************
7. Happenings
*************

Conference on Design of Circuits and Integrated Systems (DCIS)
Palacio de la Magdalena, Sanstander, Spain
November 19-22, 2002
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05cm0AD

SynTest Seminar on SoC Test Cost Reduction
DoubleTree Hotel - Irvine Spectrum, Irvine, CA
Wednesday, November 20, 2002
9.30 a.m. to 1.00 p.m., followed by lunch
To register, please contact Marc Brodnansky at
brodnansky@syntest.com or call 310-265-1304

DesignCon 2003
Santa Clara Convention Center, Santa Clara, CA
January 27-30, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05cn0AE

Design and Verification Conference and Exhibition
(DVCon, formerly HDLCon)
Doubletree Hotel, San Jose, CA
February 24-26, 2003
http://lists.planetee.com/cgi-bin3/flo?y=eOYK0DJhFR0BSK05co0AF

EDA ALERT e-NEWSLETTER CONTACTS

===============================

EDA Technology Editor, Electronic Design: David Maliniak
mailto:dmaliniak@penton.com

Advertising/Sponsorship Opportunities:
Bill Baumann, bbaumann@penton.com

=========================

To subscribe send a blank email to:
mailto:EDA_Alert_Sub@lists.planetee.com
To unsubscribe send a blank email to:
mailto:EDA_Alert_Unsub@lists.planetee.com
Penton's e-Newsletter homepage:
http://lists.planetee.com/cgi-bin3/flo?y=eNOj0DJhFR0C4C0Jvu0Ah

===============================
Copyright 2002 Penton Media Inc.