Facing The Challenge Of Adding RF And Mixed-Signal IP To SoCs

As CMOS technologies scale to greater densities, the ability to design and integrate complex and sensitive mixed-signal and RF intellectual property (IP) is becoming a reality. In fact, RF and analog/mixed-signal (RF-AMS) IP content is viewed as the next great enhancement to system-on-a-chip (SoC) design. But so far, very few products using this level of integration have been announced. This article steps through several key obstacles in the path of designers trying to integrate aggressive RF-AMS IP. It gives an overview of the issues pertaining to the process design kit (PDK), design, and CAD areas.

As an example, the demanding requirements for evolving network chip complexity cause new implementation challenges. Often, designers take an evolutionary approach toward developing large network system chips. Figure 1 shows a generic flow of integration as process technology migrates. The possibilities for complex RF-AMS IP integration have become very real, especially with the advent of advanced RF-CMOS processes.¹

For networking, integrating high-speed (3- to 10-Gbit/s) custom digital serial links is a leading requirement. This definitely requires state-of-the-art design and implementation methodologies.

When discussing RF-AMS IP, it's important to define the terms, mainly because some confusion clouds this area. Some key characteristics include:

• Requirement for IP migration/targeting: Top-down design is necessary.
• Multiple feedback loops between analog and digital blocks: Chip-wide functional design and verification is very important.
• Tight constraints on floorplanning: Analog blocks need constraints.
• Numerous custom analog, digital, and standard cell digital blocks: Many are imported from different design groups or IP vendors.
• High-performance analog blocks: They are sensitive to noise and linearity requirements (wireless).

Note that although this list isn't complete or mandatory in defining RF-AMS, it is indicative of the issues that designers face.

CAD Design Flows: Figure 2 shows a challenging RF-AMS IP integration problem. At first, the design can be viewed as a distinct set of blocks—data converters, a DSP, and an RF power amp. Designers may be inclined to design these blocks independently and assume successful integration. This is the typical approach taken today, mainly due to the lack of CAD tools that handle both the digital issues (with the associated capacity issues) and the RF-AMS issues.

But inspect the design more closely and the simulation and physical-design problems should become apparent. For instance, the design has multiple simulation domains that must be cosimulated—RF (power amp), mixed-signal (data converters), and register transfer level (DSP).

Figure 3 is a high-level CAD methodology for designing analog blocks in large SoC designs. The diagram shows two CAD flows. One flow is for the SoC design (left), including the need for analog-aware capabilities throughout. The second flow represents the RF-AMS IP design (right) with complex components, such as mixed-signal simulation and handling of accurate interconnect parasitic extraction, including transmission-line modeling.² The RF-AMS IP is designed, then imported back into the SoC design flow. Some interesting points to notice in the figure are:

• The diagram reveals the need for chip-wide "mixed-signal AHDL" simulation, and then the requirement for further simulation once the IP blocks have been integrated using FastSpice simulators. Standards like Verilog-AMS and VHDL-AMS have recently emerged and are key to developing new mixed-signal simulation engines. The issue of RF cosimulation, as required in this design, hasn't yet been fully tackled in the CAD world.
• Floorplanning, sometimes called physical design planning, is automated today for designing block-based digital ASIC and SoC designs. But the integration of RF-AMS IP brings an urgent need for analog-aware constraints to be implemented in the system. Furthermore, constraints must be passable from the SoC design CAD framework to the RF-AMS IP design CAD framework—and vice versa.
• Once the RF-AMS IP has been designed, it needs to be "packaged" to produce certain views/abstracts for integration into the larger design. (Figure 3 lists these generically, and References 3 and 4 provide more specific details to RF-AMS IP integration.) IP packaging is a very significant piece of the whole design flow because it bridges the RF-AMS IP design stage to the SoC integration stage.

As CMOS technologies scale to greater densities, the ability to design and integrate complex and sensitive mixed-signal and RF intellectual property (IP) is becoming a reality. In fact, RF and analog/mixed-signal (RF-AMS) IP content is viewed as the next great enhancement to system-on-a-chip (SoC) design. But so far, very few products using this level of integration have been announced. This article steps through several key obstacles in the path of designers trying to integrate aggressive RF-AMS IP. It gives an overview of the issues pertaining to the process design kit (PDK), design, and CAD areas.

As an example, the demanding requirements for evolving network chip complexity cause new implementation challenges. Often, designers take an evolutionary approach toward developing large network system chips. Figure 1 shows a generic flow of integration as process technology migrates. The possibilities for complex RF-AMS IP integration have become very real, especially with the advent of advanced RF-CMOS processes.¹

For networking, integrating high-speed (3- to 10-Gbit/s) custom digital serial links is a leading requirement. This definitely requires state-of-the-art design and implementation methodologies.

When discussing RF-AMS IP, it's important to define the terms, mainly because some confusion clouds this area. Some key characteristics include:

• Requirement for IP migration/targeting: Top-down design is necessary.
• Multiple feedback loops between analog and digital blocks: Chip-wide functional design and verification is very important.
• Tight constraints on floorplanning: Analog blocks need constraints.
• Numerous custom analog, digital, and standard cell digital blocks: Many are imported from different design groups or IP vendors.
• High-performance analog blocks: They are sensitive to noise and linearity requirements (wireless).

Note that although this list isn't complete or mandatory in defining RF-AMS, it is indicative of the issues that designers face.

CAD Design Flows: Figure 2 shows a challenging RF-AMS IP integration problem. At first, the design can be viewed as a distinct set of blocks—data converters, a DSP, and an RF power amp. Designers may be inclined to design these blocks independently and assume successful integration. This is the typical approach taken today, mainly due to the lack of CAD tools that handle both the digital issues (with the associated capacity issues) and the RF-AMS issues.

But inspect the design more closely and the simulation and physical-design problems should become apparent. For instance, the design has multiple simulation domains that must be cosimulated—RF (power amp), mixed-signal (data converters), and register transfer level (DSP).

Figure 3 is a high-level CAD methodology for designing analog blocks in large SoC designs. The diagram shows two CAD flows. One flow is for the SoC design (left), including the need for analog-aware capabilities throughout. The second flow represents the RF-AMS IP design (right) with complex components, such as mixed-signal simulation and handling of accurate interconnect parasitic extraction, including transmission-line modeling.² The RF-AMS IP is designed, then imported back into the SoC design flow. Some interesting points to notice in the figure are:

• The diagram reveals the need for chip-wide "mixed-signal AHDL" simulation, and then the requirement for further simulation once the IP blocks have been integrated using FastSpice simulators. Standards like Verilog-AMS and VHDL-AMS have recently emerged and are key to developing new mixed-signal simulation engines. The issue of RF cosimulation, as required in this design, hasn't yet been fully tackled in the CAD world.
• Floorplanning, sometimes called physical design planning, is automated today for designing block-based digital ASIC and SoC designs. But the integration of RF-AMS IP brings an urgent need for analog-aware constraints to be implemented in the system. Furthermore, constraints must be passable from the SoC design CAD framework to the RF-AMS IP design CAD framework—and vice versa.
• Once the RF-AMS IP has been designed, it needs to be "packaged" to produce certain views/abstracts for integration into the larger design. (Figure 3 lists these generically, and References 3 and 4 provide more specific details to RF-AMS IP integration.) IP packaging is a very significant piece of the whole design flow because it bridges the RF-AMS IP design stage to the SoC integration stage.