Monolithic Analog-to-Digital Converters (ADCs) have long been a hotbed of activity. And now the speed demons among these ICs are really coming into their own, pushing the performance envelope and expanding their domain into new applications. High-speed ADCs manufactured in both high-end and mainstream processes are boosting conversion rates across the full range of ADC accuracy.
The fast ADC's ability to digitize higher signal rates pushes digital signal processing closer to the beginning of the signal chain, allowing system designers to reap the benefits of higher integration associated with digital design.
Beyond pumping up sampling speeds, semiconductor vendors are focusing on application-specific requirements, which call for higher levels of integration, reduced power consumption, and a migration path to higher levels of precision. Still another trend is the deployment of low-voltage differential signaling (LVDS), for either a parallel or serial interface, as an option for the digital outputs. Chip manufacturers are exploiting LVDS' ability to maintain high dynamic performance at high conversion rates, to lower EMI, to reduce pin counts and package sizes, and to allow more flexible partitioning of system designs.
Just a few years ago, the "high-speed" label applied to any ADC specifying a conversion rate of 1 Msample/s or greater. Today, 10-Msample/s (MSPS) performance would more likely be considered a minimum for high-speed devices. That definition encompasses a host of ADCs, ranging from 8-bit flash ADCs with sample rates in the gigahertz range to 14-bit pipeline ADCs with performance at or near 100 MSPS.
Within this spectrum, performance also varies with the semiconductor process. In the past, the highest sample or conversion rates were achieved with converter chips fabricated in bipolar, biCMOS, or silicon-germanium processes. Then, about 18 to 24 months later, similar performance would be reached in CMOS.
In general, transitioning to CMOS reduced power consumption dramatically while only requiring modest tradeoffs in some specifications, such as signal-to-noise ratio (SNR). As a result, the CMOS chips represented mainstream performance, while biCMOS, bipolar, and other high-end process chips targeted high-performance applications.
To some extent, these generalities still hold true, but the distinctions are less clear. In the past, the transition from bipolar or biCMOS to CMOS involved a jump to finer-line geometries that yielded lower power dissipation (as well as smaller die and package size) without a supply change. Yet as the transition was made to 0.35-µm CMOS, now a mainstream process for high-speed ADCs, the supply voltage dropped from 5 to 3.3 V.
So today, as chip developers look to port their high-performance ADC designs to even finer line geometries, the redesigns are a little harder because of the shift to lower voltages, such as 2.5 V at 0.25 µm and 1.8 V at 0.18 µm. These advanced processes have the potential for higher performance. But converter development either takes longer because of the supply change or requires additional development effort (that is, more design engineers doing chip development), which raises cost. Meanwhile, biCMOS processes have undergone improvements to lower their power dissipation. Together, these changes have blurred the lines separating monolithic ADCs fabricated in biCMOS and CMOS. In the future, the best high-speed performance may even be achieved from the start in pure CMOS processes.
Nevertheless, a look at high-speed ADC performance today still shows clear divisions between mainstream CMOS and other processes. Costly 8-bit flash ADCs fabricated in bipolar processes currently achieve conversion rates of as high as 1.5 Gsamples/s. In contrast, 8-bit pipeline ADCs built in mainstream CMOS achieve only up to 250 MSPS. That's at considerably lower power levels and less cost than the faster flash converters.
Pipeline architectures from 10 to 14 bits are generally used with chips built in either biCMOS or bipolar processes for highest performance and CMOS for lower cost and power. At 10 bits, a biCMOS pipeline converter may run as high as 250 MSPS, whereas a mainstream CMOS version may go about as fast as 170 MSPS. At 12 bits, biCMOS is at about 200 MSPS, while the mainstream CMOS variation reaches perhaps 80 MSPS. At 14 bits, biCMOS pipeline ADCs achieve about 100 MSPS, but just 80 MSPS if implemented in CMOS.
Monolithic Analog-to-Digital Converters (ADCs) have long been a hotbed of activity. And now the speed demons among these ICs are really coming into their own, pushing the performance envelope and expanding their domain into new applications. High-speed ADCs manufactured in both high-end and mainstream processes are boosting conversion rates across the full range of ADC accuracy.
The fast ADC's ability to digitize higher signal rates pushes digital signal processing closer to the beginning of the signal chain, allowing system designers to reap the benefits of higher integration associated with digital design.
Beyond pumping up sampling speeds, semiconductor vendors are focusing on application-specific requirements, which call for higher levels of integration, reduced power consumption, and a migration path to higher levels of precision. Still another trend is the deployment of low-voltage differential signaling (LVDS), for either a parallel or serial interface, as an option for the digital outputs. Chip manufacturers are exploiting LVDS' ability to maintain high dynamic performance at high conversion rates, to lower EMI, to reduce pin counts and package sizes, and to allow more flexible partitioning of system designs.
Just a few years ago, the "high-speed" label applied to any ADC specifying a conversion rate of 1 Msample/s or greater. Today, 10-Msample/s (MSPS) performance would more likely be considered a minimum for high-speed devices. That definition encompasses a host of ADCs, ranging from 8-bit flash ADCs with sample rates in the gigahertz range to 14-bit pipeline ADCs with performance at or near 100 MSPS.
Within this spectrum, performance also varies with the semiconductor process. In the past, the highest sample or conversion rates were achieved with converter chips fabricated in bipolar, biCMOS, or silicon-germanium processes. Then, about 18 to 24 months later, similar performance would be reached in CMOS.
In general, transitioning to CMOS reduced power consumption dramatically while only requiring modest tradeoffs in some specifications, such as signal-to-noise ratio (SNR). As a result, the CMOS chips represented mainstream performance, while biCMOS, bipolar, and other high-end process chips targeted high-performance applications.
To some extent, these generalities still hold true, but the distinctions are less clear. In the past, the transition from bipolar or biCMOS to CMOS involved a jump to finer-line geometries that yielded lower power dissipation (as well as smaller die and package size) without a supply change. Yet as the transition was made to 0.35-µm CMOS, now a mainstream process for high-speed ADCs, the supply voltage dropped from 5 to 3.3 V.
So today, as chip developers look to port their high-performance ADC designs to even finer line geometries, the redesigns are a little harder because of the shift to lower voltages, such as 2.5 V at 0.25 µm and 1.8 V at 0.18 µm. These advanced processes have the potential for higher performance. But converter development either takes longer because of the supply change or requires additional development effort (that is, more design engineers doing chip development), which raises cost. Meanwhile, biCMOS processes have undergone improvements to lower their power dissipation. Together, these changes have blurred the lines separating monolithic ADCs fabricated in biCMOS and CMOS. In the future, the best high-speed performance may even be achieved from the start in pure CMOS processes.
Nevertheless, a look at high-speed ADC performance today still shows clear divisions between mainstream CMOS and other processes. Costly 8-bit flash ADCs fabricated in bipolar processes currently achieve conversion rates of as high as 1.5 Gsamples/s. In contrast, 8-bit pipeline ADCs built in mainstream CMOS achieve only up to 250 MSPS. That's at considerably lower power levels and less cost than the faster flash converters.
Pipeline architectures from 10 to 14 bits are generally used with chips built in either biCMOS or bipolar processes for highest performance and CMOS for lower cost and power. At 10 bits, a biCMOS pipeline converter may run as high as 250 MSPS, whereas a mainstream CMOS version may go about as fast as 170 MSPS. At 12 bits, biCMOS is at about 200 MSPS, while the mainstream CMOS variation reaches perhaps 80 MSPS. At 14 bits, biCMOS pipeline ADCs achieve about 100 MSPS, but just 80 MSPS if implemented in CMOS.