IP Rations Dynamic And Static Power In Generic 130-nm ASICs

An intellectual-property (IP) platform reduces dynamic and static (leakage) power in mobile chips built on generic 130-nm process technologies.

From Virtual Silicon Technology, the Mobilize platform adds an nMOS sleep device to each standard cell. In sleep mode, leakage is cut by more than 250×. Toggling sleep mode takes as little as 20 ns, and data-retention flip-flops prevent loss of state. And, dynamic power can be cut by more than 50% through real-time voltage-and frequency-scaling.

The platform is available for license download on the company's Web site.