Maintaining Signal Integrity Enhances ADC Circuit Performance

A Typical Drive Circuit
A representative drive circuit for a high-speed ADC has an RC configuration at the amplifier's output and in its input attenuation (Fig. 2). Although this particular circuit is designed to drive the ADC12281 12-bit, 20-Msample/s converter, the techniques are applicable to all sampling ADCs.

The overall gain of this circuit is unity. It has a nominal offset of +1.0 V. So an analog input signal of 2 V p-p centered at 0 V can be presented to the ADC as a 2-V p-p signal centered at +1.0 V.

The supply voltages to the amplifier driving the ADC should be high enough to avoid "headroom" problems. Headroom refers to the minimum voltage that must be maintained between the maximum signal peak and the power-supply rails in order to avoid distortion.

These problems arise because amplifiers typically lose gain and bandwidth as the output signal approaches the power-supply rails. The headroom requirement increases with signal frequency. A capacitive load, such as the input of a CMOS ADC, causes output-current requirements to rise with frequency (Fig. 3).

A lot can be done to enhance circuit performance through thoughtful use of the driving amplifier. A future article will focus on clock and ADC digital-output-connection considerations that minimize noise.