As the appetite for speed and broadband increases with emerging wireless access and networking applications, designers seek integrated analog front ends that must cope with the stringent and complex demands of multimode and multicarrier signals in forthcoming communications systems. Besides integrating all requisite analog-to-digital and digital-to-analog converters (ADCs and DACs), amplifiers, and other analog and mixed-signal functions on one chip, they must deliver performance that's comparable to state-of-the-art standalone devices.
To keep the cost to a bare minimum, these devices must be built on a low-cost leading-edge CMOS process. This isn't a trivial task. Add to that job the challenge of packing these devices on a single die, while pushing the performance envelope to a new height and keeping power consumption within budget. Such a device must be housed in a miniature low-cost package too.
To address these conflicting requirements and many other issues in upcoming fixed wireless, wideband 3G and 4G wireless communications systems, designers at Analog Devices Inc. have developed a family of high-performance integrated mixed-signal front ends, labeled MxFE. The latest member to join this broadband series is the AD9862, a high-performance monolithic solution for dual receive and dual transmit channels (Fig. 1). The chip reaches an unprecedented level of integration that greatly simplifies product design.
"To ensure that this integrated front end meets both cost and performance criteria of the single-chip solution, it was optimally partitioned based on these issues, and not along analog and digital boundaries," comments Joe DiPilato, Analog Devices' product line manager for communications-specific integrated products. All necessary peripheral functions are implemented on-chip to cut the overall system cost. Using the AD9862 on a mainstream digital 0.35-µm CMOS process achieves low cost.
Attaining the end objectives wasn't a frivolous task. "Several clever techniques are combined with process advances to accomplish the performance goals," asserts Iuri Mehr, senior design engineer for ADI's high-speed converter group.
To minimize crosstalk, analog and digital paths are well isolated. A nonepitaxial CMOS substrate provides reasonably high impedance. Spacing between blocks and tight diffusion guard rings, Kelvin-connected to power-supply pads, grants sufficient isolation to reduce noise and minimize analog-to-analog coupling. Consequently, the highest noise spur is more than 75 dB below the full-scale signal level. Meanwhile, the crosstalk levels between analog receive channels or between transmit and receive paths is below −85 dBc. So, a signal-to-noise and distortion (SINAD) ratio of 66 dBc (typical) results for the receive path for an input frequency of 6 MHz. The transmit path exhibits similar performance.
Using differential signals and providing separate analog and digital supply pins addresses the digital-to-analog coupling problems. Carefully selecting power-supply pins and appropriate distances between digital blocks also alleviates problems associated with the digital-to-digital coupling.
Splitting the upconversion of the transmit signal into fine and coarse tuning restrains power dissipation. While fine tuning employs a slower clock rate, the coarse tuning stage takes place prior to the DAC. Implementing a direct digital synthesizer (DDS) sets fine-tuning resolution to 1/226 of the DAC update rate, or 1.9 Hz for a 128-Msample/s DAC rate. Coarse tuning follows, where a more straightforward fDAC/4 or fDAC/8 frequency translation is performed. Running most of the circuitry at only one fourth of the DAC update rate significantly cuts overall power consumption.
At the logic level, power is managed by selecting the clock rates on a block-by-block basis and keeping logic activity to a minimum. Although this complicates clock generation and block interfaces, it greatly reduces the power in the active blocks. This is further aided by optimizing many arithmetic operations necessary in a signal-processing path and employing clever circuit techniques.
A redesigned register cell minimizes total gate load on the clock trees, curtailing the number of buffers needed to distribute good clocks. By refining the layout, the number of interconnects driven by these trees was reduced, further lessening the switched load. Consequently, the maximum power consumption, with both receive and transmit sections running, is 1.5 W at a 3.30-V supply.
Front-End Processor: The AD9862 incorporates dual 12-bit 64-Msample/s ADCs and 14-bit 128-Msample/s DACs, all optimized for the signal path of a broadband radio transceiver. This dual-converter architecture allows the AD9862 to accommodate either baseband I and Q signals, or diversity data, in both the receive and transmit paths.
In addition, it provides on-chip a complete set of communications-specific signal-processing and auxiliary functions. These include auxiliary converters, clock-generation circuitry, programmable gain amplifiers (PGAs), digital filtering, direct-digital synthesizer (DDS) tuning, image rejection, gain and offset correction, and digital mix/upconversion circuitry.