The circuit described here uses hardware instead of software routines and multiple I/O ports to select multiplexer channels in a data-acquisition system. It features an 800-ksample/s 14-bit ADC (U1), which receives and converts signals from an 8-channel multiplexer (U2) (see the figure). Three of the four output bits from a dual 4-bit binary counter are used to select a multiplexer channel. A power-on or processor-generated active high signal applied to U3’s CLEAR pin resets the counter, selecting multiplexer channel 0.
After clearing the counter, the multiplexer’s channel selection input is 000. This connects the channel 0 input to U1’s S/H input. The falling edge of the convert start signal forces the ADC’s sample -and-hold to acquire and hold the selected multiplexer signal. The rising edge of CONVST clocks the channel-selection counter. To ensure complete acquisition, CONVERT should be low for 300 ns.
As CONVST pulses increment the counter from 000 to 111, each multiplexer channel is individually selected, its input signal applied to U1’s analog input, and an A/D conversion is initiated. After the multiplexer cycles through all eight input channels, the counter rolls over to zero and the process repeats. At any time, the input multiplexer channel can be reset to 0 by applying a logic high pulse to U3’s CLEAR pin.