Designer-Directed Routing
With the shape-based routing system, the design process can be interactive and iterative. If something is obviously wrong, the designer can stop the automatic routing and adjust the floorplan, the routing costs, or other rules?or even route a particular section by hand?and continue with the auto routing. This simply isn't possible with grid-based routing.
Designers can also use push- aside routing on an individual net to add their own experience. On line design rule checking (DRC) and persistent connectivity can help with this type of manual routing .
All of these advantages compensate for the fact that each net is routed individually . It's slower than the grid-based approach, but doesn't involve multiple iterations to converge on a solution. Individual routing of the nets also allows the designer to interact with the process, which isn't possible with the grid-based approach.
The shape-based approach works at the manufacturing resolution of the reticles used in masks, rather than at a coarse wire pitch. Having a tighter resolution makes it possible to use more of the chip area effectively, producing a higher-efficiency, cost-effective die that' s easier to manufacture (Fig. 3).
Integrating Analysis Tools
Because all of the design data is available during the routing process using shape-based algorithms, the real-time parasitics and signal- integrity analysis becomes part of the assessment analysis and is tied directly into the DRC tools. As a result, the routed path meets the design requirements from the first attempt.
Even when one track is pushed aside to make room for new tracks, the change is incorporated into the routing process. New decisions in the auto router take this into account because it uses the underlying design database. That' s not to say post-layout analysis tools and iterations aren't needed. Instead, they're used primarily to check the results, rather than to cause new iterations.
Applications
Analog and mixed-signal designs aren't the only ones benefiting from this approach. It's become popular with embedded- memory companies like Hynix and Elpida.
Elpida identified peripheral-logic routing as the most time-consuming activity. In this case, rows of standard or custom cells are positioned beside the design's memory cores, and it uses the tool in its 0.11-µm flow for DRAM designs.
This approach is particularly suited to designs that involve extreme- aspect- ratio cell areas (often 30 times as wide as they are high), limited numbers of routing layers (normally two or three), and a large fraction of signals traveling a significant distance. Thus, it's good for DRAM, SRAM, flash, and imaging- sensor designs (Fig. 4).
Design For Manufacturing (DFM)
Once an automated tool is adopted, other tools can be integrated into the router to help with DFM. T he adopted tool is then able to easily add in new rules for etching and photolithography, such as width and length-based spacing rules, and maximum spacing rules.
One of these tools automatically handles layout ? tidying? and ? smoothing.? This involves removing ugly and redundant wiring patterns, which reduces the number and length of routing segments, cuts down the number of vias, and increases the spacing between the tracks. The tool can also identify and cure process ? antennas.?
Another tool analyzes yield risks in the design, such as tightly spaced tracks and single-cut vias. Other tools then automatically push those tracks apart and try to change single-cut vias to double vias for better-yielding versions.
Because the tool doesn't work to a grid, it can make very good use of the available area on each routing layer. It's possible, then, for some designs to use fewer routing layers than that required by other tools . This significantly shrink s the manufacturing cost of the chips involved.
Another DFM concern is metal density. Both etching and planarization processes used in manufacturing require an even density of metal to be left across the chip, even if there' s no wiring in some areas of the design. The tool can balance density by adding patches of metal in sparse areas of the chip, and by making ?slots? in existing wide tracks such as power and ground lines.
Engineering Change Orders (ECOs)
The incremental push- aside capability of shape-based routing is a key advantage in reducing the time taken to incorporate ECOs engineering Change Orders . If devices must be added or removed, it can be done locally by pushing tracks aside and re routing them without having to reroute large areas of the design. This means that changes have only local consequences, so it' s likely that the process will converge rapidly. Many grid-based routers can only handle ECOs by performing large-scale rerouting of the design.
The shape-based approach has also been extended into other tools. For example, it's included in the full automatic placement of cells into placement regions to generate suitable floorplans for driving the placement engine, as well as in automatic power ring and mesh generation.
Analog design has struggled to find tools that can effectively automate the design process. Shape-based routing offers significant advantages for time-to-yield and DFM for analog, mixed-signal, and embedded memory designs.
Routing individual nets with full, real-time analysis significantly reduces the time to produce a design and delivers a cost-effective, high-yielding die. Even better, designers can still use their expertise by interacting with the tool, bringing the best of both the automated and the handcrafted worlds. That's the way to hit the tighter time-to-market and cost requirements facing designers today.