Reducing Noise-Generation Sources
Use a balanced current-steering instead of voltage-switching logic family if possible. This type of gate doesn't put large switching transients onto the power rails. Outputs are taken differentially as a matched set, and the complementary outputs produce less noise. Current-steering logic isn't commonly used in large CMOS designs. Power consumption issues from the constant currents would become problematic at much lower gate counts than those of conventional CMOS circuits.
With conventional digital CMOS, other noise-reduction techniques are available. Selective controls can shut down all switching functions or digital sections not presently in use. Internal core logic should minimize the drive strength of gates—just enough to do the job. Many mixed-signal designs don't need to approach maximum clock rates. Consequently, minimum drive-strength gates are applicable in many cases.
Developers of digital cell libraries should consider the aggressive use of substrate tie-downs and n-well tie-ups within close proximity of all transistors. Inspecting most digital cell libraries reveals suitable contacts for latch-up issues, although not for substrate noise.
Due to their large external loads, I/O drivers generate large surge currents when switching. The drivers using the lowest necessary drive strength will generate less noise. Faster rise times lead to higher-frequency noise and more problems with parasitic capacitance and inductance of interconnects.
High-voltage-swing, off-chip drivers can often be eliminated in favor of reduced-swing outputs, differential voltage outputs, or current-steering differential outputs. I/O drivers employing a controlled voltage rise/fall time produce lower-bandwidth noise and reduce current transients.
If the analog system is a sampled (discrete time) system, it's preferred that the circuit have only a single clock. What's aimed at here is the avoidance of beat-frequency and mixing products in the system. Multiple clocks of different frequencies and varying phase can produce a very unpredictable noise environment.
Single-clock systems will have noise products at the clock and all of its harmonics. Multiple clocks produce the same set of harmonic noise components for each clock. They can have the sum and difference of all the frequency components too. The broad scope of analog intermodulation products can be problematic.
Analog circuits that switch large transient currents should be avoided wherever possible. Rather than turning currents on and off, they can be redirected by a current-steering method. When turning one switch off, turn another on. That allows switching of currents, while much smaller transients are seen outside of the circuit (Fig. 6). The circuit with the single switch will cause current "steps" on the power supply and turn the current source on/off. Less transient noise is caused by this two-switch system.
There will be some variance between two widely spaced grounds on an IC. Connecting a signal between these will produce signal noise because of ground noise. For nondifferential signals, some reduction in ground noise can be realized by placing the ground connection near the signal source (Fig. 7).
The circuit of Figure 7a will have ground noise added to the signal at the output of the op amp. In contrast, the circuit of Figure 7b should reduce the effects of ground noise. It has the added benefit of common-mode noise coupling to the signal path, so the noise is reduced by the common-mode rejection ratio of the op amp.
As previously stated, long signal paths should be avoided for analog signals. But when necessary, this remote ground technique should produce improved results. In conjunction with shielding, local filters, and amplifier bandwidth limiting, it will often provide adequate performance.
Digital systems generate a large amount of noise near the clock edges. With many high-speed logic circuits, transition switching associated with the clock "settles out" soon after the clock edge, remaining quiet until the next clock edge. If the clock is low enough in frequency, some "quiet time" is available between clock edges.
Of course, digital circuits can be designed to transition on only one edge of the clock. ICs have been designed to take advantage of this, where the analog sampling happens on the rising edge of the clock and the digital clocking occurs on the falling edge. Also, quiet time periods can be created for analog sampling and other noise-sensitive functions. There have been IC designs that used a fraction of the time for low-noise analog signal processing and a fraction of the time for digital processing.
As previously mentioned, trying to address the noise problem after design and fabrication can be very costly because of the time and money spent on redesign efforts. Most noise problems aren't seen in simulations. This is because parasitic elements and interconnect impedance aren't modeled. Ideal power/ground simulation models have been used in their place.
Circuit design decisions that include noise immunity as a primary concern are more likely to be a success. Keeping the analog system fully differential is important. This reduces sensitivity to common-mode noise on signals, and noise on power and ground.
Building as much noise immunity into the system as possible is suggested. Noise suppression; shielding; guard rings; internal and external filtering; talker and listener separation; and power, ground, and substrate stability need to be included in the design. No single item will completely eliminate noise issues. Removal of the loudest talker invariably leads to the discovery of the next loudest noise source. But, a distributed approach to noise immunity through the methods described in this article can reduce the issue to a tolerable level.
Naturally, the mention of noise issues always evokes discussion. Comments, opinions, and additional methods are always welcome!