Wring Out Power Through Balance
Extracting maximum power out of a given die size also is the thrust at UltraRF. To achieve that, designers there have developed a unique die architecture that permits balanced power distribution and combining of power without resorting to a two-layer metal system. Using this proprietary architecture, it is possible to scale small device structures producing large die without loss in critical parameters, such as gain and efficiency, Quinn explains. Presently, it offers single-die 1-GHz LDMOS at 90 W (CW) output, and single-die 2-GHz LDMOS at 60 W (CW). All of its devices utilize gold metallization for the highest RF performance and maximum MTF.
Increasing output power, minimizing voltage-threshold drift, and reducing hot-carrier injection through process enhancement is on Hitachi Semiconductor's design board. From about 110 W peak power at 2.14 GHz, Hitachi is planning to increase to 150 W by the middle of this year. Also, it is investigating techniques to substantially improve the hot-carrier effect of its 2-GHz parts. To guarantee the specifications on its data sheets, Hitachi subjects its devices to accelerated life testing.
Meanwhile, university laboratories around the world continue to modify the RF LDMOS structure to squeeze more juice out of a smaller die. And, they're doing so with much greater reliability. To boost output-power capability by roughly 35%, researchers at the Institute of Microelectronics and National University of Singapore have jointly developed techniques to cut large parasitic feedback capacitance by 40%, as well as hot-carrier injection by 70%. These results were detailed at the last International Electron Devices Meeting (IEDM).
Both the feedback capacitance and hot-electron injection into the gate oxide are major obstacles in conventional LDMOS devices. While the parasitic feedback capacitance limits the device's power-gain characteristics, the hot-carrier effect degrades the structure's current-carrying ability. The hot-carrier effect becomes more prominent at high voltages and reduced gate lengths. Since the LDMOS device is utilized in RF power amplifiers, the gate and drain are biased at high voltages, forcing the device to operate at high electric field while drawing high current. To achieve operations over 2 GHz, the gate length must be shrunk. Both of these conditions contribute significantly to hot-carrier degradation.
To overcome these drawbacks, Singapore researchers have modified the drain sector. By implementing a two-step lightly doped drain (LDD), they have shown that the parasitic feedback capacitance (CSI) and the on-resistance can be cut simultaneously. Additionally, a thermal oxide spacer is used to minimize gate/LDD1 overlap to cut COX, another contributor to feedback capacitance. This combination of a two-step LDD with an inherent spacer enables the developers to slash both COX and CSI to obtain nearly a 40% reduction in overall parasitic feedback capacitance, according to the University of Singapore paper given at IEDM.
Similarly, to improve the power-added efficiency (PAE) of the silicon LDMOS transistor at low supply voltages, researchers at Hitachi ULSI Systems Co. have scaled the MOSFET's gate width. By implementing a thin-gate bird's-beak technique to keep oxide thickness to 10 nm, the researchers achieved a 60% PAE at 1 W of output power and 2-GHz operation.
LDMOS devices have moved up the performance ladder in the last few years to displace bipolar and challenge GaAs devices in RF power-amplifier solutions for wireless base-station infrastructure applications. However, they're still trailing behind GaAs in efficiency and gain. Lower cost certainly is a big advantage with silicon LDMOS. To maintain its edge and address the cost issues, GaAs suppliers are migrating to larger wafers.
Wring Out Power Through Balance
Extracting maximum power out of a given die size also is the thrust at UltraRF. To achieve that, designers there have developed a unique die architecture that permits balanced power distribution and combining of power without resorting to a two-layer metal system. Using this proprietary architecture, it is possible to scale small device structures producing large die without loss in critical parameters, such as gain and efficiency, Quinn explains. Presently, it offers single-die 1-GHz LDMOS at 90 W (CW) output, and single-die 2-GHz LDMOS at 60 W (CW). All of its devices utilize gold metallization for the highest RF performance and maximum MTF.
Increasing output power, minimizing voltage-threshold drift, and reducing hot-carrier injection through process enhancement is on Hitachi Semiconductor's design board. From about 110 W peak power at 2.14 GHz, Hitachi is planning to increase to 150 W by the middle of this year. Also, it is investigating techniques to substantially improve the hot-carrier effect of its 2-GHz parts. To guarantee the specifications on its data sheets, Hitachi subjects its devices to accelerated life testing.
Meanwhile, university laboratories around the world continue to modify the RF LDMOS structure to squeeze more juice out of a smaller die. And, they're doing so with much greater reliability. To boost output-power capability by roughly 35%, researchers at the Institute of Microelectronics and National University of Singapore have jointly developed techniques to cut large parasitic feedback capacitance by 40%, as well as hot-carrier injection by 70%. These results were detailed at the last International Electron Devices Meeting (IEDM).
Both the feedback capacitance and hot-electron injection into the gate oxide are major obstacles in conventional LDMOS devices. While the parasitic feedback capacitance limits the device's power-gain characteristics, the hot-carrier effect degrades the structure's current-carrying ability. The hot-carrier effect becomes more prominent at high voltages and reduced gate lengths. Since the LDMOS device is utilized in RF power amplifiers, the gate and drain are biased at high voltages, forcing the device to operate at high electric field while drawing high current. To achieve operations over 2 GHz, the gate length must be shrunk. Both of these conditions contribute significantly to hot-carrier degradation.
To overcome these drawbacks, Singapore researchers have modified the drain sector. By implementing a two-step lightly doped drain (LDD), they have shown that the parasitic feedback capacitance (CSI) and the on-resistance can be cut simultaneously. Additionally, a thermal oxide spacer is used to minimize gate/LDD1 overlap to cut COX, another contributor to feedback capacitance. This combination of a two-step LDD with an inherent spacer enables the developers to slash both COX and CSI to obtain nearly a 40% reduction in overall parasitic feedback capacitance, according to the University of Singapore paper given at IEDM.
Similarly, to improve the power-added efficiency (PAE) of the silicon LDMOS transistor at low supply voltages, researchers at Hitachi ULSI Systems Co. have scaled the MOSFET's gate width. By implementing a thin-gate bird's-beak technique to keep oxide thickness to 10 nm, the researchers achieved a 60% PAE at 1 W of output power and 2-GHz operation.
LDMOS devices have moved up the performance ladder in the last few years to displace bipolar and challenge GaAs devices in RF power-amplifier solutions for wireless base-station infrastructure applications. However, they're still trailing behind GaAs in efficiency and gain. Lower cost certainly is a big advantage with silicon LDMOS. To maintain its edge and address the cost issues, GaAs suppliers are migrating to larger wafers.