Single Op-Amp Peak Detector Features Signal Accumulation

Figure 1 demonstrates a one-way switched-capacitor gain stage circuit, performing a voltage gain of A_O = ­C1/C2 only during the decreasing trail of the input signal V_i (with V_J = 0). During the positive signal variations, the output doesn't change, thereby implementing an incremental peak-detector and accumulator circuit.

This device can be used to measure the amplitude of noisy periodic signals with low peak-to-peak voltages. The input signal is accumulated for a certain number of cycles (N_C) to obtain a proper output voltage (V_O). The amplitude of the input signal can be derived by simply dividing V_O by the number of cycles. This reduces any noise in the measurement.

After the reset transistors M1 and M2 are turned off, the circuit works as a normal inverting gain stage for every negative input variation. During positive voltage variations, the output node V_O doesn't change and the feedback is guaranteed by diode D1—avoiding op-amp saturation. The signal path occurs along the feedback path C2-D2, where C2 holds the charge packets and D2 prevents removal of the integrated signal from C2 during the positive input-voltage variations. This operation can be repeated until a proper output signal change is obtained. The total output voltage variation can be expressed as:

where N_C is the number of cycles applied to the input and V_PP is the negative peak-to-peak voltage variation of the input signal within each period.

Figure 2 shows the circuit's output-voltage variation for 10 cycles of a sinusoidal input signal with an amplitude of 10 mV and a frequency of 100 kHz. The measured output variation is 200 mV, which is in accordance with the above equation. Note that the higher the number of accumulation cycles (N_C), the lower the noise contribution at the output voltage.

This circuit can also be used as a phase detector between two signals (V_I and V_J) having the same amplitude. When the two signals are applied at inputs V_I and V_J, the amplifier accumulates only the negative difference between the two signals. Figure 3 shows the circuit's response to different phase-shift conditions. For a 0° phase shift, the resulting output voltage is 2A (where A is the signal amplitude of V_I and V_J), which is the maximum anticipated signal. For 180° of phase shift, the output voltage is zero, as expected.