The beating heart of mixed-signal processing is delimited by the clock devices that slice the analog world into digital events. Like our own hearts, we don’t pay much attention to them unless something goes wrong. When it does, it pays to know something about the various ways these silicon tickers can act up.
JITTER
In choosing clock chips for high-performance data converters, the most critical datasheet characteristic is jitter, which translates to phase noise in the frequency domain (Fig. 1). You can look at the jitter as uncertainty in the placement of the data conversion. But from an analytical standpoint, it may be useful to look at that phase noise as a limitation on signal-to-noise ratio (SNR). Really high-performance, high-speed converters require clocks with RMS jitter below 200 fs.
For converter applications, broadband RMS additive jitter is a good specification to compare. For networking applications, specific offset bandwidths, such as 12 kHz to 20 MHz or 5 to 80 MHz, are typically specified. Either way, be sure to check the conditions for measurement. A faster slew rate, for example, will result in better SNR in data-converter applications. Additionally, measuring over a restricted band of offsets reduces jitter magnitude.
To achieve the highest SNR, you should choose the lowest possible jitter under your conditions. If the number of outputs isn’t high enough, add fan-out clock buffers of less than 100 fs to avoid inserting too much additive jitter into the clock chain.
BASIC GOOD HOUSEKEEPING
“Tidy is as tidy does,” they say. If you want to avoid clock-related problems, you have to keep the clock signals on the printed-circuit board (PCB) traces where they belong and off of adjacent traces and power-supply lines. That means good layout with proper terminations bypassing where needed, as well as edge control.
For clock distribution, the most common methods for terminating transmission lines are series, parallel, Thevenin, and ac terminations (Fig. 2). Series termination occurs at the driver end of the line. The other methods deal with reflections at the receiver end.
To make a series termination, connect the resistor in series with the driver output pin and the trace. Choose the resistor value so it and the output impedance of the driver add up to the characteristic impedance (Z0) of the transmission line.
Series termination and the driver output impedance add up to be less than the line characteristic impedance, as it is for most transistor-transistor level (TTL) or low-voltage CMOS (LVCMOS) drivers. Series termination does not waste power by shunting some current to ground, which is a good thing. But it does have a negative impact on the rise/fall time of the clock transition, so there is some increase in jitter susceptibility.
In parallel termination, the clock input of the chip that is being driven is tied to ground with a resistor that has a value of x times Z0. The line is properly terminated, but current through the resistor represents a certain amount of power loss. That leads to the Thévenin termination, in which there are two resistors at the input to the driven device, one to VCC and one to ground. There is less power loss, though at the cost of adding an extra part.
That leaves ac termination, in which a capacitor blocks dc power flow, resulting in low losses but with the penalty of an increase in propagation delay. In ac termination, resistor values are generally sized larger than Z0 – 75 Ω, rather than 50 Ω, which creates a small mismatch yet offers the advantage of reducing leakage at the input stage of the receiver. There are tradeoffs to consider in choosing a capacitor. It’s generally sized larger than 50 pF. That’s considered sufficient to sink the ac current. However, larger values up to 120 pF allow faster clock transitions.
RADIATED INTERFERENCE AND SPREAD-SPECTRUM CLOCKING
Noise doesn’t just affect the circuit being clocked. It can affect the world at large, or at least other electronic devices within a few meters of your design. Curiously, for dealing with radiated electromagnetic interference (EMI), we use spread-spectrum clocking (SSC), which is all about deliberately adding jitter to a clock.
With SSC, you pseudo-randomly dither the clock frequency to spread its energy spectrum over a wide frequency band, rather than have its energy concentrated at the clock fundamental frequency and its odd harmonics. This reduces the peak energy, which often allows the design to meet the requirements of the application. Those requirements may include the FCC part 15 (Title 47 CFR Part 15) regulation that applies to “unintentional radiators.” Essentially, it provides a profile of allowable field strength across the RF spectrum.
Not everyone is happy with the engineering decisions that were made in establishing the Part 15 limits because they don’t specify a maximum level of emitted energy. With a spread-spectrum radiator, the measuring equipment in effect averages the energy across a period of time while the interference from class A or B (B has the more stringent spec) dithers with the switching frequency.
As one Electronic Design reader recently complained, “We’ve traded birdies at specific frequencies for a general hiss across the entire band.” As a practical matter, electronic equipment that is sensitive to a narrow band of frequencies sees less interference while equipment with broadband sensitivity to EMI experiences more interference.
Nevertheless, Part 15 is what we have, and spread-spectrum clocking is what allows clocks and switching supplies to meet Part 15 requirements. Given that, design parameters for spread spectrum clocking include modulation index (d), modulation frequency (fm), modulation profile, and spread type.
Modulation index is the frequency variation (spread) of the clock signal, expressed as a relative percentage of the nominal clock frequency, fc. For example, ±1% spread means that a 100-MHz clock is jittering pseudo randomly between 99 and 101 MHz. The greater the value d, the more reduction in EMI, but the greater the jitter in the clock signal.
Modulation frequency refers to the rate at which the clock frequency varies between fc and (1-d)fc. Usually, fm is a little greater than 30 kHz, which keeps it out of the audio band but well below the system clock.
The modulation profile (Fig. 3) describes how the clock frequency is modulated. In the time domain, the profile that provides the most evenly distributed spectrum is patented by Lexmark International. It resembles the shape of a Moorish arch or a “Hershey’s Kiss.” More often, one sees a triangular “Shark Fin” sweep profile, which results in some rippling at the ends of the frequency spectrum.