The ABCs Of ADCs

Real-world applications require real-world connections. Generally, that means an analog signal is being digitized somewhere in the system so a microprocessor, ASIC, or FPGA can gather data and make some decision. If you’re new to data converter concepts or if it’s been a long time since your last analog class, the datasheet and design specifications and considerations can seem alien or even outright confusing. So what do all of those acronyms mean, and why should you care about spurious-free dynamic range (SFDR) or anti-aliasing?

PRIMARY SELECTION CRITERIA
In general, most designers seem to care about several primary criteria when selecting an analog-to-digital converter (ADC). Specs such as power consumption may be very important when designing a next-generation, portable, low-power data-acquisition system. But in most cases, engineers start looking at parts based on:
• Digital interface (SPI, I²C, parallel, etc.)
• Resolution (the amount of effective bits needed)
• Speed of conversion required
• ADC architecture
• Input structure (what the analog signal looks like)

Secondary selection criteria usually include power-consumption considerations (active and sleep mode) and reference-voltage integration. They also frequently include system-friendly features, such as an integrated FIFO for the digital data, an integrated programmable gain amplifier (PGA), or general-purpose I/O connected to the serial bus.

DIGITAL INTERFACE CHOICES
The digital part of an ADC is usually a primary criterion. That’s because the digital system implementation may be limited by the availability of certain interface types as well as required data-transfer rates.

For example, when interfacing an ADC to your favorite microcontroller (with your 10 years of legacy code), you may only have an I²C interface available on the ADC. Or for higher-speed or higher-resolution ADCs, a parallel interface may be the easiest way to rapidly transfer a large amount of data for applications such as digital filtering that might be running inside an FPGA.

Each of the three main interface types—two-wire or I²C, three-wire or SPI, and parallel—offers advantages and disadvantages when they’re offered on precision ADCs. High-speed ADCs (greater than 10 Msamples/s) also may offer low-voltage differential signaling (LVDS) as an interface for high-speed serial connection to an FPGA.

The two-wire or I²C interface offers low pin count and, as a result, small package size. In other words, only two pins are used for data transfers. This allows for maximum channel counts in very small packages. For instance, an eight-pin package provides two pins for the interface, two pins for power, and four pins for analog inputs. The MAX11613 four-channel, 12-bit ADC from Maxim, for example, comes in a micro-max eight-pin package.

The small form factor of these devices makes them ideal for consumer applications and system power-monitoring applications. (I²C also is very similar to power-management SMBus protocols.) In addition, space-constrained applications using three-axis accelerometers and gyroscopes such as game controllers and dead-reckoning systems often use I²C-based ADCs due to their high channel count per unit area.

However, these interfaces provide slow data transfer, and they’re difficult to isolate. The data pin on I²C interfaces is a bidirectional open-collector pin. As such, it may become difficult to use the interface with systems that require (optical) isolation for noise isolation or safety, such as medical applications. In addition, I²C based systems can be slow. Their maximum data-transfer rates usually don’t go above 3.4 Mbits/s.

Three-wire interfaces and SPI deliver a full-duplex, high-speed bus that supports 100 Mbits/s (in theory). Also, if multiple ADCs (or other SPI devices) are on a single bus, you can cascade, say, eight MAX11040 parts for 32 channels on a single isolated SPI bus for power-grid applications. Furthermore, SPI supports easy and cost-effective (optical) isolation. This approach is relatively easy to implement in FPGAs as well. It requires more pins than I²C, though.

Parallel interfaces provide high throughput plus a simple logic control interface, which is good for FPGAs. Unfortunately, they also require a high pin count.

RESOLUTION
So how many bits do you need? This trivial question can be complicated by inherent ADC errors, signal amplitude, least-significant-bit (LSB) step-size, and dynamic range requirements. Simple system voltage and current measurements may require only an 8-, 10-, or 12-bit ADC, for instance. But measuring a sensor in a classic resistive bridge configuration may require a 24-bit sigma-delta ADC device to detect small signal changes in a very large overall signal.

The resolution often is quoted in dB (decibels), which provides an approximation of the overall signal-to-noise ratio (SNR) of the ADC (and hence how small a signal it can resolve from the sensor or system noise floor).

Each bit of resolution is approximately 6 dB. Therefore, theoretically, a 12-bit ADC should have an approximately 72-dB SNR. In reality, many factors limit SNR, and a 12-bit ADC with an SNR of 70 dB or greater would be considered good.

ADC suppliers quote this figure of merit in one of two common forms: effective number of bits (ENOB) or signal to noise and distortion (SINAD). These two forms are related. One definition for ENOB is:

ENOB = (SINAD – 1.76)/6.02

where all values are in dB. SINAD is the ratio of the wanted signal (the fundamental) to the sum of all distortion and noise products, after the dc term is removed. Also:

SINAD = (rms SIGNAL/rms NOISE)

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