Running an ADC at higher sample rates for shorter periods may be a good option for periodic data acquisition. Clearly, for mission-critical systems, this technique may not work. In that case, choosing an ADC with the lowest active power consumption makes the most sense.
ADC ARCHITECTURE
Five basic ADC architectures are used for most commercially available ADCs today: flash (or parallel), successive approximation register (SAR), sigma-delta (or delta-sigma), dual slope, and pipeline.
The flash or parallel ADC includes 2N – 1 high-speed comparators (Fig. 5). These converters typically offer the highest conversion speed and are used where power consumption isn’t a primary concern. Flash ADCs are usually more expensive than most other converter approaches, and their chip area and power consumption generally increase exponentially with resolution.
SAR is a binary search approach using a DAC. A comparator forms the basis for these popular ADCs (Fig. 6). After a sample of the analog input is taken, usually by sampling the signal with a capacitor, the signal is successively compared to the output of a DAC to determine each successive register bit. The SAR register sets the DAC input, and the result converges bit-by-bit successively. Conversion time increases with resolution.
Mainstream devices offer medium to high resolution up to 18 bits and an upper range of about 5 Msamples/s at lower resolutions. SAR devices are low-power and have small form factors. Accuracy depends on internal component matching (on-chipbased capacitor arrays). The SAR-based ADC architecture reigns supreme in the marketplace, though sigma-delta devices have become increasingly popular, especially for low-speed, highprecision, sensor-based applications.
SAR devices can be found in a wide array of applications. They include motor control, battery fuel gauges, power-supply and system monitoring, high-speed sensors in automotive power-train and safety applications, rotational sensors, proximity sensors, accelerometers, gyroscopes, protective relays for power systems, and power-amplifier subsystems for communications.
The sigma-delta (or delta-sigma) architecture allows for the implementation of high-resolution to ultra-high-resolution (16 to 24 bits) converters, which are typically low- to medium-speed devices (Fig. 7). In the sigma-delta approach, the converters oversample a signal and then use DSP techniques to shape and filter noise, which achieves excellent SNR in the area of signal interest. It also offers a small die area and typically low speed, usually below 200 ksamples/s.
Simpler analog circuitry is used with a complex internal DSP for filtering and noise shaping. This leads to excellent linearity in the ADC’s response as well as very low harmonic distortion, which are critical for measuring very small signals. The most common application for sigmadelta ADCs other than audio digitization (audio codecs) is the measurement of very small signals from physical sensors. Temperature, weight, pressure, acidity, flow rate, and strain are some of the common physical phenomena digitized by these parts.
The dual-slope architecture provides ultra-low power for measuring slow-moving signals. These dual-slope parts support high resolutions (18 bits). An unknown voltage is integrated, and the value is compared against a known reference that ramps. Sigma-delta devices have replaced this technology in most high-precision applications.
The pipeline architecture supports high speeds to more than 100 Msamples/s and up to 16 bits, with less power than flash. These ADCs are small, pipelined parallel structures in which each stage only works on a couple of bits (Fig. 8). Parallelism increases throughput (speed) at the expense of power and latency (delay). This is a very popular architecture for most high-speed data-acquisition applications, such as RFbased data-acquisition systems.
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