Measuring key characteristics of high-speed pulses such as frequency, amplitude, and pulse width for simultaneous pulses that overlap in time has long been an issue in design. To solve that problem, engineers developed and refined the monobit receiver1.
The system includes RF signal shaping and filtering functions, a latched comparator (which is a single-bit analog-to-digital converter, or ADC), a demultiplexer to interface the high-speed digital data to commercially available FPGAs, and advanced digital-signal-processing (DSP) algorithms to extract the frequency and phase information.
The high-speed latched comparator (monobit ADC) is the key enabler of the monobit receiver design. Its function is to accurately digitize the input signal at the correct times. Two of the key specs for the monobit ADC are input analog bandwidth and thermal offset voltage.
Input analog bandwidth determines the maximum signal frequency that can be sampled. It is important in a bandpass sampling configuration, where the signal frequency can be greater than the sample frequency (see “Bandpass Sampling").
Thermal offset voltage is analogous to the input hysteresis for high-speed measurements. In the monobit receiver application, where the monobit ADC must make accurate decisions relative to a threshold voltage for input signals with varying histories in the time domain, it is important to minimize the dependency of the threshold voltage on past signal conditions.
Such variations of the threshold voltage can be seen as a thermal offset voltage, because the threshold voltage is shifted by thermal asymmetries that result from the electrical asymmetries in the differential datapath in the monobit ADC. This thermal offset voltage depends on the input data, and it is typically more significant than the dc hysteresis.
The output from the monobit ADC is a high-speed digital signal at many gigabits per second. To interface it to commercially available FPGAs that generally have low-voltage differential signaling (LVDS) I/O at up to 1 or 2 Gbits/s, a high-speed demultiplexer is needed to deserialize the high-speed bit stream into parallel lanes at lower speed. For example, a 1:8 demultiplexer can demultiplex a 10-Gbit/s highspeed bit stream to interface to an FPGA at 1.25 Gbits/s.
The single-bit digitization in a monobit receiver enables sampling at very high speeds. However, the tradeoff is that quantizing to only one bit generates a large number of spurious frequencies. Therefore, DSP is required to resolve the difference between the real signal frequencies and the spurious frequencies, via thresholding or other techniques. An additional requirement is to perform this signal processing in real time, within the power constraints of the system.
A MONOBIT RECEIVER PROTOTYPE
Figure 1 illustrates a design example of a monobit receiver developed by LNX Corp. for frequency measurement over the 0.5 to 18 GHz band. Target characteristics appear in Table 1.
The LNX Monobit DIFM (Digital Instantaneous Frequency Measurement) is based on a very high-speed monobit ADC. Multiple channels are required to cover the full 0.5- to 18-GHz band. However, the LNX design uses bandpass sampling techniques or direct digital down conversion to eliminate intermediate, mixerbased down conversions. All of the digital processing is performed in a single FPGA.
RF FRONT END
The RF front end contains:
• A limiting amplifier: The limiting amplifier has an operating bandwidth of 0.5 to 18 GHz. The loss of the frequency multiplexer, including the power divider and filters, will be approximately 12 dB. The power output of the limiting amplifier is less than +10 dBm.
• A frequency multiplexer: The partitioning of the 0.5 to 18 GHz frequency spectrum depends on the maximum sample rate allowed by the digitizer coupled with the ability to handle the demultiplexed data rate.
• Digitization and demultiplexing: The high-speed digitization is performed using Inphi’s 1385DX 12.5 Gbit/s 1:8 demultiplexer, which has a high-sensitivity latched comparator front. The 1:8 demultiplexer can be clocked at rates up to 12.5 Gbit/s.
The input amplitude to the demultiplexer is 500 mV p-p (–2 dBm). This sets the output power requirement of the limiting amplifier. The demultiplexer provides a demultiplexed 8-bit value and FS/16 data clock. For example, if the clock/sample rate for each channel is 8.192 GHz, then the data rate after demultiplexing is 1.024 Gbits/s. The clock is aligned so clock transitions occur in the middle of data transitions, simplifying clocking at the destination.