Low-Load Efficiency

Cycle-skipping is another way to improve efficiency at light loads. In skip mode, a new cycle is initiated only when the output voltage drops below the regulating threshold. The switching frequency is proportional to the load current. In applying this approach in a supply with synchronous rectification, the driver must open the switch each time the current through the inductor reverses, so the MOSFET’s body diode blocks the reverse current.

Yet another approach is to supply the load using multiple supplies whose clocks operate at different phases, shedding or adding capacity as needed. In practice, this allows each parallel switcher in a multiphase dc-dc converter to operate at a relatively low frequency.

When combined, though, they produce the responsiveness and regulation performance of a single-phase, very high switching-frequency converter without the switching losses associated with higher frequencies. Another advantage is that, by staggering the phases, the inherent output ripple is smoothed out.

At light loads, it makes sense to shut down some phases, because the efficiency of individual converters is greater at higher loads. As the total load increases, dormant phases can be brought back on line. The tricky part here lies in phase synchronization and balancing—adjusting the relative phases on the fly.

Interestingly, to achieve the fastest transient response, it can make sense to provide the ability to drive all clock phases in sync. In some regulators, normally, clock phases are evenly distributed to minimize the combined ripple. But it is possible to switch to a mode in which the clocks to all phases are time-aligned, effectively paralleling the inductors to reduce total inductance and increase transient ramp time.

MOSFET EFFICIENCY
So far, this analysis has concentrated on controller design. What about losses in the switching MOSFETs? Broadly, MOSFET losses can be attributed to channel and body-diode conduction, switch-transitions, gate drive loss, output capacitance, and reverse recovery loss. For simplification, these can be reduced to conduction losses, switching losses, and “others.”

For any particular MOSFET technology, conduction losses are inversely proportional to MOSFET size, while switching losses are directly proportional to MOSFET size. Optimzing efficiency is a matter of balancing the two.

Switching losses arise from total gate charge (Q_G), pre-threshold gate-to-source charge (Q_GS1), post-threshold gate-to-source charge (Q_GS2), and gate-to-drain charge (Q_GD). The important losses, though, occur as the MOSFET turns on—that is, as the gate drive voltage transitions from its threshold voltage (V_t) to its plateau voltage (V_Plat). After that, switching losses (Fig. 5) are virtually zero. Hence, Q_GS2 and Q_GD are the principal contributors to switching loss. (Some data sheets summarize these as “switching charge,” Q_sw.)

For both the top and bottom switch, the object is to examine the operating conditions and select a MOSFET that, for those conditions, exhibits essentially the same conduction losses as switching losses. That provides reasonable assurance of near-minimum total loss.

The objective is first to calculate up two characteristics for the MOSFET: switching losses per unit switch charge (expressed in W/nc) and conduction losses per unit drain-source on resistance (expressed in W/mΩ) and take their ratio. The second step is to compare that to R_DS(on)/Q_sw. The closer the two ratios, regardless of their actual values, the lower the losses.

For the high-side FET, switching loss per unit switch charge is:

(V_In x I_Out/I_Drive + Q_G/Q_sw x V_Drive)f_sw

Conduction loss per unit drain-source on resistance is:

(I_Out² + I_pp²/12) x (V_Out/V_In)

For the low-side FET, substitute V_fd, the voltage drop of the FET’s body diode in the first expression, and use (1 – V_Out/V_In) in the second. Otherwise, I_Drive is the drive current, roughly, (V_Gate – V_{Threshold)/(RDrive + RGate). VDrive is the source voltage for driving the gate.}