Superior jitter performance is ensured by "a secret ingredient." The innovative circuit is a special digital PLL in the CMU. It uses a new architecture that incorporates a DSP loop filter. Silicon Labs calls it DSPLL. This patent-pending architecture greatly simplifies how optical transmission equipment is designed (Fig. 2).
In a standard analog PLL, the phase-frequency detector (PFD) compares the two inputs and develops an analog error signal, which an active RC low-pass network filters. Typically, the RC filter components are off chip as their integration is difficult and designers usually want to select values to optimize performance. These external components invariably pick up noise, which translates into jitter. Temperature changes, aging of these parts, and power-supply variations also influence jitter. While a ground shield around these components can minimize jitter, it doesn't eliminate it completely.
The DSPLL approach uses an analog PFD, but the analog error signal is sent to a special analog-to-digital converter. The digitized output is then filtered in a DSP low-pass filter. This process doesn't require any external components. The LC voltage-controlled oscillator (VCO) has a digital control input. The DSP algorithm generates a digital control value, which is used to adjust the frequency. With this ar-rangement, the VCO output frequency can be frozen by storing the digital control value. Plus, the DSPLL is totally insensitive to power-supply and temperature variations, as well as to any board noise.
The DSP filter is set up so that one of two loop bandwidths can be selected—wideband or narrowband. The BWSEL input line picks the bandwidth.
In the wideband mode, the bandwidth is 50 kHz. This bandwidth is implemented when a very low jitter source provides the reference clock. In this way, the DSPLL more closely tracks the reference source, providing the best possible jitter performance. On the other hand, the narrowband loop bandwidth is 12 kHz. This setting offers better filtering of the reference clock to help reduce jitter, and it permits operation with a noisier reference clock.
One benefit of the narrowband mode is that it enables the Si5600 to support Sonet/SDH-compliant loop-timed operations. This mode is chosen by the LPTM line made high. The transmit clock and the data timing are derived from the recovered clock output of the CDR. The recovered clock is divided by 16 and used as the reference source for the transmit CMU. What results is a transmit clock and data signal that's locked to the received data. The narrowband setting is recommended for this type of operation.
Built into the Si5600 are two loopback test modes that greatly facilitate diagnosis, measurement, and troubleshooting. The diagnostic loopback mode establishes an output from the serializer output to the deserializer input. This allows comparison of the low-speed parallel TXDIN data with the RXDIN parallel data. This mode is entered by making —DLBK low.
By making —LLBK low, the line loopback mode is entered. Doing so provides a loopback path from the high-speed serial receive input to the high-speed serial transmit output, allowing the comparison of the input clock and data to the transmitter data output.
To give designers maximum flexibility, Silicon Labs supplies a complete family of OC-192 and OC-48 parts. The receiver portion of the Si5600 is available as the Si5530. It contains the limiting amplifier, CDR, as well as 1:16 deserializer and related circuits. Also, the transmitter comes as the Si5540 with the built-in DSPLL CMU, the 16:1 serializer, FIFO, and associated circuits. Silicon Labs also recently announced its OC-48 transceiver ICs, which have similar architectures. The Si5100 is a transceiver with 16-bit buses, while the Si5110 has 4-bit buses.
A related chip using the DSPLL circuitry is the Si5364. It's a port card IC that generates four low-jitter clocks with outputs at either 19, 155, or 622 MHz with less than 1 ps of rms jitter. It also accommodates conversion to or from FEC clock frequencies. This chip provides Sonet Stratum 2, 3, 3E, and SMC compliance and features fully hitless switching.
Price & Availability
The Si5600 is sampling now with full production scheduled for the fourth quarter. It's priced at $555 each in 1000-unit quantities. The Si5530 and Si5540 are sampling now and run $270 each in 1000-unit quantities. The Si5100 and Si5110 sell for $157 and $148 each, respectively, at the 1000-unit level. And, the Si5364 is now available in production lots. In 1000-unit quantities, it costs $99.95.
Silicon Laboratories, 4635 Boston Lane, Austin, TX 78735; (877) 444-3032; fax (512) 416-9669; www.silabs.com.
Superior jitter performance is ensured by "a secret ingredient." The innovative circuit is a special digital PLL in the CMU. It uses a new architecture that incorporates a DSP loop filter. Silicon Labs calls it DSPLL. This patent-pending architecture greatly simplifies how optical transmission equipment is designed (Fig. 2).
In a standard analog PLL, the phase-frequency detector (PFD) compares the two inputs and develops an analog error signal, which an active RC low-pass network filters. Typically, the RC filter components are off chip as their integration is difficult and designers usually want to select values to optimize performance. These external components invariably pick up noise, which translates into jitter. Temperature changes, aging of these parts, and power-supply variations also influence jitter. While a ground shield around these components can minimize jitter, it doesn't eliminate it completely.
The DSPLL approach uses an analog PFD, but the analog error signal is sent to a special analog-to-digital converter. The digitized output is then filtered in a DSP low-pass filter. This process doesn't require any external components. The LC voltage-controlled oscillator (VCO) has a digital control input. The DSP algorithm generates a digital control value, which is used to adjust the frequency. With this ar-rangement, the VCO output frequency can be frozen by storing the digital control value. Plus, the DSPLL is totally insensitive to power-supply and temperature variations, as well as to any board noise.
The DSP filter is set up so that one of two loop bandwidths can be selected—wideband or narrowband. The BWSEL input line picks the bandwidth.
In the wideband mode, the bandwidth is 50 kHz. This bandwidth is implemented when a very low jitter source provides the reference clock. In this way, the DSPLL more closely tracks the reference source, providing the best possible jitter performance. On the other hand, the narrowband loop bandwidth is 12 kHz. This setting offers better filtering of the reference clock to help reduce jitter, and it permits operation with a noisier reference clock.
One benefit of the narrowband mode is that it enables the Si5600 to support Sonet/SDH-compliant loop-timed operations. This mode is chosen by the LPTM line made high. The transmit clock and the data timing are derived from the recovered clock output of the CDR. The recovered clock is divided by 16 and used as the reference source for the transmit CMU. What results is a transmit clock and data signal that's locked to the received data. The narrowband setting is recommended for this type of operation.
Built into the Si5600 are two loopback test modes that greatly facilitate diagnosis, measurement, and troubleshooting. The diagnostic loopback mode establishes an output from the serializer output to the deserializer input. This allows comparison of the low-speed parallel TXDIN data with the RXDIN parallel data. This mode is entered by making —DLBK low.
By making —LLBK low, the line loopback mode is entered. Doing so provides a loopback path from the high-speed serial receive input to the high-speed serial transmit output, allowing the comparison of the input clock and data to the transmitter data output.
To give designers maximum flexibility, Silicon Labs supplies a complete family of OC-192 and OC-48 parts. The receiver portion of the Si5600 is available as the Si5530. It contains the limiting amplifier, CDR, as well as 1:16 deserializer and related circuits. Also, the transmitter comes as the Si5540 with the built-in DSPLL CMU, the 16:1 serializer, FIFO, and associated circuits. Silicon Labs also recently announced its OC-48 transceiver ICs, which have similar architectures. The Si5100 is a transceiver with 16-bit buses, while the Si5110 has 4-bit buses.
A related chip using the DSPLL circuitry is the Si5364. It's a port card IC that generates four low-jitter clocks with outputs at either 19, 155, or 622 MHz with less than 1 ps of rms jitter. It also accommodates conversion to or from FEC clock frequencies. This chip provides Sonet Stratum 2, 3, 3E, and SMC compliance and features fully hitless switching.
Price & Availability
The Si5600 is sampling now with full production scheduled for the fourth quarter. It's priced at $555 each in 1000-unit quantities. The Si5530 and Si5540 are sampling now and run $270 each in 1000-unit quantities. The Si5100 and Si5110 sell for $157 and $148 each, respectively, at the 1000-unit level. And, the Si5364 is now available in production lots. In 1000-unit quantities, it costs $99.95.
Silicon Laboratories, 4635 Boston Lane, Austin, TX 78735; (877) 444-3032; fax (512) 416-9669; www.silabs.com.