Equipment designers, particularly those
involved with communications and high-end
data, face the constant challenges of increasing
data rates and greater packaging densities.
In turn, these requirements are driving development needs for
compact, high-speed components, including connectors.
DESIGN CHALLENGES
High-speed computing and networking system designers
have the benefit of choosing from cost-effective, high-speed
backplane connectors that utilize edge-coupled and shield-less
technology since the introduction of the AirMax VS backplane
connector system in 2003. This technology delivers high signal
density while exhibiting low insertion loss and crosstalk,
allowing systems to scale differential signals up to 12.5 Gbits/s
without necessitating a redesign of the basic platform.
Breaking the dependence on metal shields to accomplish
consistent high-speed electrical performance also provides
design flexibility. Users can allocate individual contacts in a connector
module to differential pairs, single-ended signals, or lowlevel
power as dictated by system needs. Options for increased
column spacing enable more signal traces on a board layer, trading
some signal density for lower layer counts and board costs
for applications not demanding maximum signal density.
These backplane connectors provide high signal density
with connectors configurable for 15 contacts per column and
2-mm column spacing, 63.5 differential pairs, or 190.5 contacts
per inch, achievable within a 25-mm card slot pitch. Lowerprofile
options provide 12 or nine contacts per column and allow
designers to achieve a card slot pitch of 20 mm or less. As systems
generate more heat due to increased numbers of processors,
additional memory, and higher signal speeds, designers may also
employ the lower-profile connectors to minimize obstructions
to airflow and significantly improve cooling efficiency.
Even with these connectors, designers now find that density
is increasingly critical. The transition from rack-mount servers
to denser blade server form factors in the data center is just
one example of an industry trend driving the need for more
efficient space utilization and improved thermal management.
Connector density now extends beyond the traditional measures
of the linear density along the edge of the daughtercard
or the connector system’s vertical profile.
For connector manufacturers to meet this need, high-speed
connector designs must maximize signal density in all three
dimensions to address the mechanical and thermal concerns of
system designers. Advances to preserve signal integrity at high
data rates are necessary to fit more differential signal pairs in a
smaller volume.
INCREASING SIGNAL DENSITY
One example addressing density requirements, the ZipLine
connector system for backplane and orthogonal midplane
applications, initially provides 18 contacts or six differential
pairs per wafer on 1.8-mm column spacing. The system also
provides 84.6 differential pairs per inch along the card edge.
Adapting the press-fit connectors to a 1.5-mm column pitch
can achieve 101.6 signal pairs per linear inch. Line extensions
to add connector configurations with nine contacts per signal
wafer will enable the connectors’ use in systems with card-slot
spacing down to 15 mm.
With the use of edge-coupled technology, increasing the
spacing between signal wafers incurs no adverse impact to
differential impedance. The larger column spacing may allow
users to reduce the number of backplane and daughtercard
layers by 50%.
POWER DELIVERY
With more multicore processors and memory, systems require
additional power delivery to daughtercards in a chassis. This is
addressable either by integrating higher-power contacts in signal
connector modules or by installing separate high-power connector
modules on the card edge. When a high-speed connector
design also provides optional power wafers in a signal module,
both signal and power contacts can fit in a single connector.
One such design features a special six-contact power wafer,
rated at 6 A per contact with an aggregate capacity to deliver up
to 36 A when a power wafer is included in a six-pair module (Fig.
1). Higher power levels are achievable by adding more power
wafers, but in doing so, the current-carrying capacity needs to
be derated accordingly. The use of a different resin color for the
power wafer gives assemblers a visual indicator to differentiate
power-signal modules from standard signal modules.
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