ORTHOGONAL MIDPLANE ARCHITECTURE
Since the emergence of orthogonal midplane
system architecture, more communications
equipment designers are adopting
this packaging scheme to accomplish direct,
efficient connections between multiple line
cards and a common switch or communications
card (Fig. 2). Vertical daughtercards
on one side of a midplane have a direct connection
to horizontal add-in cards on the
opposite side of the midplane.
Orthogonal midplane headers are
installable back-to-back and oriented at
90° to each other. The headers’ signal pins
share the same vias in the midplane, providing
a direct connection while eliminating
the need for connecting traces. Reducing
the number of backplane signal traces also
reduces design complexity. Some orthogonal
midplane interconnects can support
differential signaling at up to 20 Gbits/s.
To enable proper registration of opposing
signal contacts in the vias, the header
design requires a different orientation of its
press-fit tails when compared to standard
backplane headers where all tails lie along
the centerline of each signal wafer. For an
orthogonal midplane header, differential signal
pair tails are offset to the left and right of
the centerline while the differential pairs in
adjacent signal wafers are offset by one contact
position. The result is a perfect match of
signal contacts, ground contacts, and plated
via holes when two headers are rotated at 90°
during back-to-back installation.
In addition to ensuring correct contact
registration, connector manufacturers
must consider the signal integrity of the
link. Most typically employ a combination
of electrical simulation and test for optimization
and performance validation, which
also yields the recommended footprint and
printed-circuit board (PCB) layout for the
subject connectors. For some orthogonal
midplane designs, these recommendations
include the use of wide antipads surrounding
the vias to minimize impedance mismatch
and the positioning of adjacent differential
pairs at 90° to minimize crosstalk.
With a six-pair, 12-column connector, a
design can include up to 72 differential pair
crossovers in a single module. With flexible
connectors, designers may also allocate
connector columns to backplane or power
wafers for product customization.
NEXT STEPS
With growing IP traffic driving demand for
aggregate bandwidth, designers continue to
test the limits of existing backplane connectors
and challenge manufacturers to develop
next-gen components. While high-speed
serial backplane links in current telecom
and datacom equipment typically fall in the
range of 2.5 to 6 Gbits/s, designers are aiming
to achieve 40 Gbits/s and higher.
To accomplish these goals, designers
must balance three components: chip
packages, multilayer backplanes and
daughtercards, and connectors. Until
cost-effective SERDES transceivers
become available, the less costly next
step may be the use of multiple parallel
lanes to achieve higher throughputs.
For example, the initial implementation of
a 40-Gbit/s Ethernet link might consist of
four high-speed serial lanes with each lane
operating at 10 Gbits/s.
Obviously, designers continue to demand
faster data links with high signal density in
small packages, which the market already
provides. But even the latest technologies
will continue to evolve, driven by the need
for ever greater speeds and density.