Some applications will continue to tap the attributes of the pipelined topology, namely high speed and high resolution at a low supply voltage. As resolution and speed are pushed to new heights, differential techniques and high-performance sample-and-hold circuits will be incorporated to drive power consumption to a new low.
Innovative designs have helped developers break the speed barrier in the successive-approximation-register (SAR) ADC domain without compromising power. As a result, last year Analog Devices (www.analog.com) released a 16-bit SAR ADC with a conversion speed of 1 Msample/s—double the previous record. That record will be broken again this year, and efforts are under way to double it again. Also, many more suppliers will join the fray, introducing faster 16-bit ADCs.
Concurrently, there is a trend to pack multiple SAR ADCs on a chip. In fact, a six-channel version with at least 500-ksample/s conversion capability is in the works, with a drive toward even more channels and faster speeds from a monolithic solution.
As usual, hybrid and board-level designs will take advantage of leading-edge converters to push their performance a step further. To justify the cost, the hybrids and boards will include all the functions needed to deliver complete solutions, with the ability to maintain ac and dc performance over an extended temperature range. This will let time- and frequency-domain applications migrate to higher-resolution ADCs with ease.
Hence, the trend is toward 18-bit designs with over 1-Msample/s sampling, while the 12- and 16-bit parts will be driven to higher frequencies. Also, dual and quad versions in a single package will be driven by applications like radar and communications.
As ADCs strive to adequately serve the appetite of the powerful digital signal processors they en-counter in today's DSP-centric solutions, the pressure to push sampling frequencies higher is even greater. Thus, be prepared to see 14-bit ADCs boasting conversion rates of 100 Msamples/s, while 10- and 12-bit versions will come with data rates as high as 200 Msamples/s. Obviously, power consumption will be a real challenge for these faster units. To address this problem, developers will exploit the benefits of low-voltage designs using fine-line CMOS and biCMOS technologies. Development work on 0.18-µm CMOS processes conducted last year will bear fruit this year and in the future.
Although the major thrust in will be toward deep- and very deep-submicron CMOS for their cost, low power, and integration advantages, many high-end applications will prefer to pay more for the superior performance of biCMOS. In fact, silicon-germanium (SiGe) bipolars will begin to play an important role in next-generation biCMOS processes. As it evolves in the next few years, it will aid in the integration of high-performance ADCs with RF front ends for many wireless and wireline communications applications. Meanwhile, methodologies and transistor technologies are under development to narrow the technology gap and fabricate these devices in the mainstream digital CMOS process. At this rate, it will not be long before the two merge on the same platform.
For motor-control and measurement applications, 8-bit microcontrollers have recently been integrated with low-end analog functions like 8- and 10-bit ADCs, general purpose operational amplifiers, and sensors. Now, developers want to incorporate medium-performance analog/mixed-signal functions on-board with the microcontrollers. So users will start to see faster 12-bit and higher-resolution ADCs, along with wideband op amps, combined with speedier 8-bit and 16-bit microcontrollers.
Analog-To-Digital Converters
Introduced in the late eighties, the delta-sigma (Δ-∑) architecture has become the norm among ADC designers. It has facilitated the integration of dense mixed-signal ICs using advanced CMOS processes. Today, it boasts 24-bit resolution at output data rates as high as 192 kHz, with developers working to deliver even higher performance at lower prices. In fact, the insatiable quest for better audio is motivating developers to adopt multibit topologies with clever dynamic element matching to further boost the ac performance and the dynamic range, while cutting power and cost.
As they begin to tap 0.25-µm and finer CMOS processes, designers will bring more functionality on-chip without compromising on power or die size.
Over time, the low-speed 24-bit chip has become a complete data-acquisition solution to effectively serve markets such as weight and temperature measurement, control, and sensing. As suppliers work to wring more performance from a miniature package, they are also adding more bells and whistles to this line of ADCs. Developers have begun to include filters to reject 50- and 60-Hz signals, even as they are pushing for conversion rates of over 40 ksamples/s. In fact, the trend is toward 100 ksamples/s. For programming, nonvolatile flash memory will be added. The addition of microcontrollers to these ADCs is also on the drawing board.
Speaking of speed, this year's International Solid-State Circuits Conference (ISSCC) will provide a quantum leap in conversion rates for 8-bit ADCs. Agilent Technologies (www.agilent.com) will demonstrate a 4-Gsample/s, 8-bit ADC in 0.35-µm CMOS with an accuracy of 6.1 effective bits at 1 GHz. Philips (www.philips.com) will unveil a 1.6-Gsample/s, 6-bit flash ADC in 0.18-µm CMOS. Agilent's 8 bitter will consume 4.6 W, and Philips' 6-bit ADC will dissipate 340 mW. Analog Devices will describe a high-performance ADC with on-chip mixer for dual-conversion superheterodyne receivers. This multibit bandpass Δ—∑ ADC with continuous-time LC and active RC resonators, including SC resonators, consumes only 50 mW and offers an unprecedented 90-dB dynamic range. Other highlights include a presentation by Maxim Integrated Products (www.maxim-ic.com), which will introduce a fifth-order, multibit Δ—∑ ADC with 14-bit resolution and a 4-MHz conversion bandwidth. Implemented in 0.18-µm CMOS, it achieves a dynamic range of 80 dB at a low oversampling ratio. In another paper, scientists at Infineon Technologies (www.infineon.com), in cooperation with the Technical University of Munich, Germany, will disclose a Δ—∑ ADC at 0.7 V.
Multichannel chips are not limited to SAR ADCs. Other architectures, like Δ—∑ and pipelined, also permit multiple functions on the same die. Depending on the demands of the application, several high-performance ADCs will be integrated on the same chip to replace multiple parts traditionally used in a multichannel application. For instance, in high-quality audio, six- and eight-channel versions of 24-bit Δ—∑ ADCs will be offered. If flexibility is important, suppliers will provide high-performance multichannel chips with the ability to operate each channel independently of the other.
See associated timeline.