We can look at how each phase of the development performed on the worst-case test loops (Fig.1). That's the HDSL2 minimum test set versus the theoretical best performance, or Shannon Theory, and against the HDSL2 standard requirements. The tests show a 6- to 10-dB margin over other DSL systems. This can be exploited to either improve reach for a given data rate, or reduce the transmission power. Thus, the line's overall crosstalk is improved and its power dissipation is reduced.
A key decision that allowed the chip set to reach these performance levels was made early on. It was to develop a proprietary AFE (Fig. 2). This allowed the company to use its mixed-signal expertise to achieve several benefits. The first, an optimal tradeoff between the digital and analog elements of the solution, led to a more efficient partitioning of the analog and digital functions. This resulted in better silicon usage, lower power dissipation, and tighter coupling between the mixed-signal and digital elements.
Next, the embedded MIPS processor can be used to optimize the performance of the AFE stage in coordination with the tuning of the digital section. This brings about a high level of end-to-end system optimization in which the digital and mixed-signal subsystems are trained in parallel to match the observed loop characteristics. This couldn't have been achieved by using standard, off-the-shelf AFEs.
Fully compliant with the HDSL2/G.shdsl standard, the AFE also is configurable for either central-office (CO) or remote applications. It supports rates from 2.304 Mbits/s down to 192 kbits/s and has fully differential analog paths.
Both the AFE's 16-bit analog-to-digital converter (ADC), as well as the 16-bit digital-to-analog converter (DAC), sample at 2 MSamples/s. A DAC and filter for adaptive echo synthesis (AES) also is included.
The transmitter has programmable attenuation control (PAC) with a 16-dB dynamic range and 1-dB resolution for HDSL/G.shdsl-compliant power backoff. The receiver's programmable-gain amplifier (PGA) has a wide dynamic range of 32 dB and 1-dB resolution. The wide range is a key enabler for the algorithmic processing.
The AFE meets HDSL2 overlapped PAM transmission with an interlocking spectrum (OPTIS) power-spectral-density (PSD) mask when interfaced with the EBS720 digital chip. OPTIS is a noise-cancellation scheme that shapes the upstream and downstream transmit spectra for maximum performance in the worst-case noise conditions that occur in either end of the loop. The AFE includes an integrated voltage-controlled crystal oscillator and comes in a 64-pin TQFP.
The EBS720 digital processing end combines the PAM transceiver, framer, and the 512-state Trellis encoder and decoder (Fig. 3). Also included are the echo canceler, precoder, feed-forward equalizer, and decision-feedback equalizer. Supporting AES as well, it too meets ANSI HDSL2 and the emerging ITU G.shdsl standards. Further, it supports rates from 2.304 Mbits/s down to 192 kbits/s. A 16-level PAM with OPTIS transmit PSD mask is used for the T1 transport in the HDSL2 mode. Additionally, the device supports fall-back modes using 2B1Q line code, as in the case of SDSL. The PSD of the transmitted signal is programmable, a feature that allows it to reduce crosstalk and interference within the binder group.
A digital control bus included in the EBS720 allows communication with the AFE. This makes possible the tuning of settings within the AFE, while allowing for power cutback and other functions as well. Plus, the chip comes with an 8-bit parallel host interface and operates off 2.5 V. Packaging is in a 120-pin PQFP.
Both the EBS720 and EBS710 are made on a standard CMOS processor. The digital section is made on a 0.25-µm processor and has a power consumption of under 1 W, while the mixed-signal end is made on a 0.35-µm processor. This runs off 3.3 V and has, on average, a power consumption of 280 mW. These power figures are for full-rate, 1.5-Mbit/s HDSL2 operation.
Of course, the total power consumed also is a function of the line drivers, which varies widely for HDSL2 versus G.shdsl. The company expects its HDSL2 consumption to be in the range of several hundred milliwatts and under 400 mW for G.shdsl, for a total that weighs in under 2 W. The next-generation chip set will be under 1.5 W/port, including the line driver.
Price & Availability
The EBS720/EBS710 combination is priced at $35 each in quantities of 10,000. It's available now.
Excess Bandwidth Corp., 10670 N. Tantau Ave., Cupertino, CA 95014; Contact Joe Grady (408) 342-2730; fax (408) 255-0066; e-mail: joe@exbc.com; www.exbc.com.