Soft-core models lack interconnect parasitic-delay information and, therefore, lack accurate timing information. The vendor might provide sample timing data for a technology. In addition, the vendor may supply a bus-functional model that simulates the core's behavior at the pins between the core and external circuitry without modeling the core's internal configuration.
Core vendors design their products as synchronous, timing-predictable logic blocks in order to guarantee operation over a range of technologies. Because behavioral or RTL simulation doesn't verify performance, you can check timing performance only after synthesizing the core to the gate level for a target technology. Then you use vendor-supplied, estimated timing delays for that technology. Accurate timing simulation can be done only after place-and-route and back-annotation of interconnect parasitics.
After you have chosen and configured your processor, decided on the peripherals and provided peripheral stubs, and picked any custom peripherals that you're going to create for this design, you face the task of implementing the internal bus structure that glues it all together. It's important that these elements be automatically generated to eliminate the chance of human error and ensure that everything will work together.
A good system design tool will generate the common elements to connect all of the peripherals to the processor, including the chip-select decoder, data return multiplexer, interrupt controller, and wait-state generator. The Nios soft-core processor for the APEX product line, for example, has a wizard included in the Excalibur development tool kit that automatically configures the peripheral bus module. It generates HDL, instantiates and connects all of the peripherals to the processor—whether they are canned or custom—and creates the necessary glue logic.
The wizard automatically generates wait states, interrupt control, variable bus sizes, and address decoding (Fig. 2). For instance, the user can indicate which peripherals interrupt the processor. For each one that does, the wizard automatically assigns an address in the interrupt lookup table and generates the corresponding interrupt control logic. Bus size converters are employed to adapt 32-bit peripherals to 16-bit configurations as necessary. This kind of functionality doesn't just dramatically shorten the design cycle. It also assures that the logic is correct the first time.
Soft-core processors present unique testing challenges. Core vendors should implement and prove the design in silicon and also prove that their products comply with industry-standard specifications. In addition, they should provide an acceptable simulation on an accompanying test bench. But because soft cores have flexible technologies and implementations, designers must provide a means for testing them in their particular designs.
For cores in HDL format, a test bench defines how to exercise the core logic's nodes after a designer embeds the core into a chip and tests the entire chip. A test bench should provide high-fault coverage for the core. At a gate-level representation, test-vector suites provide the same function of exercising the core with high-fault coverage.