As previously mentioned, the original architecture for the 21160 was inspired by radar processing requirements that heavily rely on performing extremely fast FFTs. With SIMD processing, the 100-MHz 21160 executes a 1024-point complex FFT in 90 µs, which is even faster than the C6701 operating at a higher clock rate of 167 MHz.
In radar processing, sophisticated signal-enhancement techniques can be used to extract very small targets, provided that the accuracy of the calculations is maintained throughout. For this reason, the extra precision offered by floating-point processors, like the 21160, proves to be a major advantage over fixed-point designs, such as the C6203.
Because there will be many processors acting in parallel to meet the processing de-mands from the many elements, the six 100-Mbyte/s interprocessor link ports are another advantage for the 21160 in this application. They can be utilized to very effectively merge signals from each of the many antenna elements to form the final image. With no built-in multiprocessing resources, the C6701 would require a significant amount of external hardware to handle these transfers.
Another reason to select the 21160 for this project is the wealth of radar software already developed for the original 21060 SHARC processor. This is fully code-compatible with the 21160.
Remote signal intelligence receiver: The third system involves a software radio requirement for a remote, standalone receiver system capable of receiving, classifying, demodulating, and storing a wide range of known and unknown transmissions. At the front end of this system is an antenna, an RF downconverter, a wideband ADC, and a digital receiver. It's important to be able to pick out a very weak signal in the presence of other large signals. For this reason, a floating-point processor is ideal. The scope of this remote receiver strongly suggests implementing a single processor, if possible.
At 1000 MFLOPS, the C6701 offers the maximum of floating-point processing power. Furthermore, the absence of multiprocessing support on the C6701 isn't a factor in this single-processor system. The large number of different demodulation and classification algorithms can be efficiently developed from floating-point routines. This provides the necessary accuracy without the lengthy software development effort to handle the scaling and optimization that a fixed-point processor would require.
The C6701 first computes an FFT using wideband output from the ADC to determine the frequencies of signals present. Next, it tunes the digital receiver to the signals of interest, again performing a spectral analysis to try to classify the modulation technique. The most probable demodulation algorithm is then performed on the narrowband signal and the output is analyzed for meaningful content. Several different demodulation schemes might have to be tested until a useful signal is obtained. If the intelligence gleaned is useful and important, it can be saved in a local hard disk along with a time and date stamp for later retrieval.
For additional savings of valuable development time, numerous third-party software library tools for the C6000 family help complete the list of required analysis and demodulation functions.
Every application will require that the system designer assign the appropriate weighting factors to the strengths and weaknesses of each DSP device under consideration. By identifying these factors early in the design cycle, and by picking the right DSP for the job, the project is much more likely to hit high marks in cost, performance, and delivery.