DRAM: Space Vs. Cost
Due to the use of DRAM technology, the chip area is considerably smaller than that of an SRAM-based CAM. It follows that it also will carry a significantly lower price. To deliver a sustained search throughput when running at a 66-MHz clock rate, the Class-IC chip employs a double-data-rate memory interface on the data load port. Because data can be transferred on both edges of the clock, the chip can perform searches with only half the number of pins required by competing solutions.
Associated with each CAM entry are a number of special bits that the memory uses to encode the type and validity of that entry. In this first-generation Class-IC family, bits for Empty, Skip, Permanent, and Age are available. Empty status is an obvious requirement for updating the table. Skip is important for managing press-allocated, but empty, locations in the CAM. It also allows the user to walk through a series of multiple matches.
Age is a single-bit indicator that's updated whenever there's a referral to an entry. By using this bit, the CAM management software knows which entries are "stale" and can purge them after a specified amount of time. The Permanent bit protects an entry against this purging due to the entry's age. The chip also handles Learning and Aging functions. That way, it can support Layer 2 bridging applications in switches.
Additional ternary CAMS are available from Lara Technologies, and SiberCore Technologies, two fairly new companies that are providing support for the network industry. Able to keep pace with the NetLogic chip at 83 million searches (either exact or longest prefix match), the LTI7010 can work with tables as large as 16,384 entries featuring entry widths as wide as 272 bits (Fig. 3). Multiple CAM chips can be cascaded to allow the construction of large tables. Up to 1 million entries are possible. Each entry is maskable on a bit-by-bit basis, permitting the user to store and compare ones, zeroes, and don't-cares in each location.
Wide-word capability—up to 256-bit words—also is offered by the SiberCAM family from SiberCore. The family has ternary longest-prefix-matching capability as well. The company claims the speed crown with its chips—up to 100 million sustained searches per second. Read and write operations don't steal search cycles, so the CAMs can deliver optimal performance.
One extra feature thrown into the SiberCAM is a low-power architecture that trims the power consumption, making it the lowest-power ternary CAM available to date. Initially, the company released two versions of its chip: one with 2 Mbits of on-chip memory, and the other with 8 Mbits of on-chip ternary CAM storage. Either can be configured in one of two different modes.
In the first, the chip is optimized for table lookup operations and employs three ports: a comparand input port, a search output port, and a non-intrusive table-management port. The second mode differs in that the chip is optimized for low pin count and the comparand and table-management ports are combined into a single port.
CAM Emulation
The use of software to emulate a CAM is the kickoff development by researchers at NeoCore. The NeoCAM virtual engine can run on a host processor and turn a bank of SDRAM into a CAM of almost any desired depth. It provides all of the capabilities and performance acceleration aspects of a traditional CAM. Plus, it adds on-the-fly capability to adjust the key width and depth.
The company offers the virtual CAM engine as a software solution, but it's also used as an ASIC solution (a chip set). Both use the same application programming interface (API). That API, part of the software-development kit, can be used to model the virtualized technology.
An alternative to CAMs comes from another relatively new company, Agere. Its APP1200 fast pattern processor provides a programmable engine capable of handling 2.5-Gbit/s data streams and process over 6 million packets/s today. The company expects the roadmap it set up to lead to packet-processing speeds of beyond 50 million packets/s and wirespeed operation at up to 20 Gbits/s.
To achieve such performance levels, Agere developed a high-level functional-protocol language (FPL) that lets designers program the fast pattern processor. The processor can then recognize and classify incoming packets based on millions of data patterns. In FPL, instructions are coded like a protocol definition language, with interspersed action statements and the ability to embed routing table information directly into the protocol code.
The chip performs complex pattern or signature recognition, and operates on the packets or cells that contain those signatures. Programs written in FPL are compiled and loaded onto the host processor for execution. The code is optimized for packet processing. Programming in FPL is much simpler than with conventional languages, such as C++.
DRAM: Space Vs. Cost
Due to the use of DRAM technology, the chip area is considerably smaller than that of an SRAM-based CAM. It follows that it also will carry a significantly lower price. To deliver a sustained search throughput when running at a 66-MHz clock rate, the Class-IC chip employs a double-data-rate memory interface on the data load port. Because data can be transferred on both edges of the clock, the chip can perform searches with only half the number of pins required by competing solutions.
Associated with each CAM entry are a number of special bits that the memory uses to encode the type and validity of that entry. In this first-generation Class-IC family, bits for Empty, Skip, Permanent, and Age are available. Empty status is an obvious requirement for updating the table. Skip is important for managing press-allocated, but empty, locations in the CAM. It also allows the user to walk through a series of multiple matches.
Age is a single-bit indicator that's updated whenever there's a referral to an entry. By using this bit, the CAM management software knows which entries are "stale" and can purge them after a specified amount of time. The Permanent bit protects an entry against this purging due to the entry's age. The chip also handles Learning and Aging functions. That way, it can support Layer 2 bridging applications in switches.
Additional ternary CAMS are available from Lara Technologies, and SiberCore Technologies, two fairly new companies that are providing support for the network industry. Able to keep pace with the NetLogic chip at 83 million searches (either exact or longest prefix match), the LTI7010 can work with tables as large as 16,384 entries featuring entry widths as wide as 272 bits (Fig. 3). Multiple CAM chips can be cascaded to allow the construction of large tables. Up to 1 million entries are possible. Each entry is maskable on a bit-by-bit basis, permitting the user to store and compare ones, zeroes, and don't-cares in each location.
Wide-word capability—up to 256-bit words—also is offered by the SiberCAM family from SiberCore. The family has ternary longest-prefix-matching capability as well. The company claims the speed crown with its chips—up to 100 million sustained searches per second. Read and write operations don't steal search cycles, so the CAMs can deliver optimal performance.
One extra feature thrown into the SiberCAM is a low-power architecture that trims the power consumption, making it the lowest-power ternary CAM available to date. Initially, the company released two versions of its chip: one with 2 Mbits of on-chip memory, and the other with 8 Mbits of on-chip ternary CAM storage. Either can be configured in one of two different modes.
In the first, the chip is optimized for table lookup operations and employs three ports: a comparand input port, a search output port, and a non-intrusive table-management port. The second mode differs in that the chip is optimized for low pin count and the comparand and table-management ports are combined into a single port.
CAM Emulation
The use of software to emulate a CAM is the kickoff development by researchers at NeoCore. The NeoCAM virtual engine can run on a host processor and turn a bank of SDRAM into a CAM of almost any desired depth. It provides all of the capabilities and performance acceleration aspects of a traditional CAM. Plus, it adds on-the-fly capability to adjust the key width and depth.
The company offers the virtual CAM engine as a software solution, but it's also used as an ASIC solution (a chip set). Both use the same application programming interface (API). That API, part of the software-development kit, can be used to model the virtualized technology.
An alternative to CAMs comes from another relatively new company, Agere. Its APP1200 fast pattern processor provides a programmable engine capable of handling 2.5-Gbit/s data streams and process over 6 million packets/s today. The company expects the roadmap it set up to lead to packet-processing speeds of beyond 50 million packets/s and wirespeed operation at up to 20 Gbits/s.
To achieve such performance levels, Agere developed a high-level functional-protocol language (FPL) that lets designers program the fast pattern processor. The processor can then recognize and classify incoming packets based on millions of data patterns. In FPL, instructions are coded like a protocol definition language, with interspersed action statements and the ability to embed routing table information directly into the protocol code.
The chip performs complex pattern or signature recognition, and operates on the packets or cells that contain those signatures. Programs written in FPL are compiled and loaded onto the host processor for execution. The code is optimized for packet processing. Programming in FPL is much simpler than with conventional languages, such as C++.