DDR FCRAM Boosts Performance In DDR SDRAM Designs

Interface And Termination: The interface specification for DDR SDRAM and DDR FCRAM is Stub Series Terminated Logic (SSTL_2), JEDEC standard, JESD8-9. SSTL_2 offers adequate output current drive to permit parallel-termination schemes, which is important for high-speed signaling. It also allows for proper termination of the bus transmission lines and reduces signal reflections. This will improve settling, lower EMI emissions, and make higher clock rates possible. A minimum termination resistance to V_TT can be used and still comply with the standard's minimum output voltages and currents.

For best performance when implementing DDR FCRAM, the single-resistor termination scheme is strongly recommended. Benefits include lower cost, simpler signal routing, reduced reflections, and improved signal bandwidth and settling.

DDR FCRAM supports four programmable SSTL_2 drive strengths, which are 4 mA (weakest), 8 mA (default), 12 mA (strong), and 16 mA (strongest). Selection is accomplished by an internal user-programmable register set. This feature allows designers to program the drive strength to suit their overall system and pc-board requirements.

In lightly loaded systems—that is, systems with few memories—where the memories are physically close to the controller, the weakest drive type may be selected to limit the driver slew rates and benefit both signal integrity and radiated emissions. Higher drive currents would better suit heavily loaded systems with more memory devices and higher capacitance.

DQS Termination: The DQS lines should be terminated with discrete resistors to V_DDQ and V_SS. This will keep noise on V_TT caused by the changing data lines from affecting DQS. These lines should be terminated with discrete resistors. This allows the termination to be adjusted independently of any other signals.

Bidirectional Line Termination: The data and DQS lines are bidirectional. To have the same levels at all receivers from all transmitters, a series resistor is required on all devices that can drive the line. The signaling standard is called series stub logic because there's a series resistor at every stub. Terminations to V_TT should be at both ends of the main bus. Resistor packs are acceptable for these terminations.

V_TT And V_REF: The V_TT supply must be able to both sink and source current. This means that a standard switching power supply can't be used without a shunt to let the supply sink current. Because each data line is connected to V_TT with relatively low impedance, this supply must be very stable.

Designers shouldn't generate V_REF with one divider routed from the controller to the memory devices. The optimal solution is to generate a local V_REF at each device. Discrete resistors should be used to produce V_REF, while resistor packs should be avoided.

Address/Control-Line Termination: Address and control lines (except for DQS lines) are unidirectional. These lines need only a series resistor at the controller. Also, these lines transfer data at half the rate of the data lines and may need less termination to function properly. Resistor packs for these terminations are acceptable.

Frequency Versus Termination: At lower frequencies, the full SSTL termination might not be needed. For point-to-point applications (one controller and one memory device per data line), both the series resistor and the resistor to V_TT may often be omitted entirely for frequencies below 160 MHz. Just the series resistor may be required for frequencies under 200 MHz. These termination reductions must be simulated and checked out to ensure that the design has an adequate margin.

Actual driver strength and board layout significantly affect the performance of these termination schemes. Several other schemes have been used successfully in point-to-point applications. The key to successfully implementing FCRAM and achieving peak performance is simulation.

Data Strobe Signal (DQS): Because FCRAM is a DDR-type DRAM, it outputs data at both the rising and falling edges of the clock. In FCRAM, the address and command signals are synchronized with the clock input, while the data pins are synchronized with the DQS signal. Data output takes place at both the DQS's rising and falling edges. DQS is in phase with the clock input of the device.

A lag may occur in the journey time for signals from the controller to the memory, and from memory to the controller due to different wiring lengths of data lines, command/address lines, and the clock (Fig. 4). This lag time makes it difficult for the receiver (memory or controller) to acquire data correctly.

Because the FCRAM performs the input/output of data at twice the frequency of the external clock, the valid data window is narrower. To eliminate this difficulty, the devices (both controller and memory) output the DQS signal. The receiver can acquire data securely by receiving the DQS signal.