DUAL CHANNELS
The newer, dual-channel data-bus architecture doubles the number of data bits by using two 64-bit data buses. This widely adopted bus basically doubles the active current associated with the DDR DRAMs. The theoretical maximum for the VTT current increases due to a higher termination load:
IVTT = (128 + 1 6) × 16.8 mA = 2.4 A
But the average worst-case current doesn't increase significantly, as it's so unlikely that both channels' I/Os will be stuck driving a one or a zero. Intel specifies this current at 1.8 A.
The VDD bus is also implemented to power the graphic memory control hub (GMCH) DDR inside of the chip set, as well as the 2.5- to 1.5-V linear regulator for the adaptive graphics processor (AGP). The exact current specifications tend to vary from one chip set and motherboard to the next. However, for the Intel Springdale chip set, the VDD bus must be able to supply 19.5 A in S0 (active) and 650 mA in S3 (suspend-to-RAM) mode.
INTEGRATED DDR CONTROLLERS
To take full advantage of the DDR memory, the dc-dc converters must comply with the DDR power and bus-accuracy requirements. This is further complicated by a myriad of timing and sequencing guidelines set forth by the instantly available PC (IAPC) specifications. Individual motherboard and chip-set manufacturers often impose unique demands on the controller. Motherboard signals S0, S3, and S5 govern the behavior of the DDR and VTT bus. The regulator is responsible for 20 A of current for the VDDQ (per the latest Intel specs) during S0, or "motherboard-active" state. It must make a smooth transition to and from the S3 or "suspend-to-RAM" state with minimal dc and ac deviations on the VDD bus.
In some implementations, the chip set will continue to draw current from the VDD bus for several milliseconds after the S3 has been asserted. The VDD bus must be able to hold the dc accuracy for that duration. Any "drop out" can be catastrophic, as that voltage is also used to retain data and refresh the DDR DRAM.
One example of such a DDR regulator and controller is the SC2616 "three-in-one" DDR controller. It's designed for the latest Intel and AMD motherboards using DDR1 or DDR2 standards. High-current synchronous gate drives are needed to ensure high-output-current capability for the switcher, while the internal VTT regulator must be able to sink and source 1.8 A using the pc board as a heatsink. The DDR controller must also adhere to Advanced Configuration and Power Interface (ACPI) timing and sequencing specifications.
Figure 3 shows a typical connection and the internal block diagram of the SC2616 DDR controller. A MOSFET, with source and drain reversed, is placed in series with the top MOSFET to prevent back-feeding the input supply during "suspend-to-RAM" mode via the top MOSFET body diode.
Power for the VDD bus is supplied from a switching buck converter, stepping down the 5-V input supply to 2.5 V. During S3, as the current is reduced, the 5-VSTBY supply provides the IDDQSTBY current via a linear regulator. When transitioning from S3 to S0, VDDQSTBY proceeds the VDDQ switcher. Thus, the synchronous MOSFET must stay "off" until the switcher takes full control of the output VDD bus to prevent current reversal in the output inductor.
Note that upon assertion of the S3 signal, the VDDQ switcher won't relinquish the bus until the input Silverbox rails drop below undervoltage lockout. This allows sufficient time for the chip-set current to diminish, maintaining the required VDDQ voltage accuracy.
The SC2616's high-speed error amplifier responds to bus transients in less than one pulse-width modulation (PWM) clock cycle. The VDD and VTT rails must be bypassed with low-ESR capacitors near the DIMMs, while the electrolytic capacitors near the dc-dc converter supply the averaged currents. Each bit must also be bypassed with a local ceramic capacitor to provide the fast burst of currents (3 A/ns).
The internal logic and latches of the SC2616 ensure reliable sequencing under all motherboard states, while three different internal thermal-shutdown circuits enable safe operation. The SC2616 reduces the overall solution cost by integrating three regulators in one low-pin-count MLP, with a copper pad for direct heatsinking to the pc board. Figure 4 shows the SC2616 timing diagram and the VDDQ, VDDQSTBY (during S3), and VTT voltages in compliance with the defined S0, S3, and S5 motherboard signals.
Other flavors of the SC2616 are available, such as the SC2614 for Intel-specific motherboards, using the Intel "glue chip" for the BF_CUT signal. The SC2615 and SC2617 controllers, which use a 3.3-V input supply, are tailored toward lower-current DDR1 or DDR2 applications, and come in an MLP package.
Recommended Reading:
Calculating DDR Memory System Power, Technical Note TN-46-03, Micron Technology.
General DDR SDRAM Functionality, Technical Note TN-46-05, Micron Technology.
JEDEC Standard SSTL_2, Dec. 2000, and JEDEC Standard SSTL_18, Oct. 2002.
Special thanks go to Scott Schaefer, applications engineering manager, Micron Technology, for his valuable contributions to this article.