These circuits can also be combined with advanced digital-DLL circuits that minimize the PHY latency (i.e., from the memory-channel clock domain to the internal clock domain of the memory controller). FlexPhase also provides for in-system timing characterization and self-test functionality, which enables aggressive timing resolutions of 2.5 ps at 3.2-GHz data rates in high-performance memory systems.
FlexPhase was built to minimize the system-level cost and complexity of routing an XDR memory system. However, FlexPhase techniques can also be used to address the clock-distribution challenges of other fly-by command/address systems, such as DDR3.
In DDR3’s fly-by topology, the time required for data, strobe, clock, address, and command signals to propagate between the controller and DRAMs is primarily affected by trace lengths propagating those signals. Clock, command, address (CCA) signals arrive at each DRAM at different times. As described in further detail below, this results in data signals being transmitted from each DRAM at different times.
FlexPhase techniques can therefore be used in the DDR3 memory-controller PHY to deskew data signals, which eliminates the offset due to the fly-by architecture in addition to any inherent timing offsets of the memory system. For example, during READ operations, the memory controller with FlexPhase circuits can reliably compensate for the difference between the transmitted control signals and the data received from each memory device.
Using a 32-bit memory bus to illustrate, the DDR3 CCA bus “flies by” the DRAMs, causing read data launch-time offsets (Fig. 4). Even if trace lengths were exactly matched, each DRAM’s data arrives at the controller at different times. Consequently, the burden rests on the controller to be smart enough to independently capture each DRAM’s reads and writes and reliably reassemble the whole 32-bit word. As stated earlier, FlexPhase circuits can be used at the controller to deskew data signals, nullifying the offset due to the fly-by clocking architecture and minimizing the latency of the 32-bit word in the PHY itself.
During WRITE operations, a similar process is performed in which the memory controller can preskew the timing delay between transmitted clock, command, and address signals and the data/strobe signals sent to each DRAM. DDR3 DRAMs include a special operational mode for write-strobe deskew, also known as “levelization,” to assist with optimal preskew timing by the memory-controller PHY. Figure 5 depicts an example of FlexPhase timing preskew used in conjunction with such a levelization mode in a fly-by memory system architecture.
In summary, the FlexPhase circuit techniques and differential signaling used by XDR memory present several system, design, and cost benefits to address the challenges faced by designers of multi-Gbps memory systems. And while DDR3’s use of fly-by command bus and clock distribution allows for higher-speed command-bus signaling with multiple DRAM loads, it creates new data-bus challenges to reliably communicate between the memory controller and the DDR3 DRAMs.
And, although DDR3 DRAMs include a special “levelization” mode to assist with write-mode deskew, the newly added complexity of the memory controller PHY is significant, especially as clock frequencies continue to increase. In such systems where the lowest cost-per-bit advantages of DDR3 are the principal design metric, FlexPhase circuit techniques that address similar concerns in XDR memory systems can be used in DDR3 memory-controller PHYs to achieve reliable multi-Gbps memory operation performance.