DSP processors optimized for motor control applications are merging the traditional control function of an MCU with the horsepower of a DSP. Plus, motor-specific functions are implemented to address a wide variety of applications. On-chip flash provides low-cost nonvolatile memory for reprogramming the device. Lately, the addition of a motor current-sensing feature to these DSPs cuts the component count and the bill-of-material costs.
Today's DSP architectures are tailored for programming in high-level languages like C and C++. Therefore, we're seeing the development of compilers and DSP architectures simultaneously to ensure that the DSP designed fully complies with the compiler for highest code efficiency. The trend will continue to get higher code efficiency until all programming is in C or C++.
Floating-point versions continue to evolve to serve applications that need precision like high-quality digital audio, imaging, and robotics, some of the latest applications moving in the direction of 32-bit precision. It's not just the horsepower, but the price-performance ratio and ease of programming that drives many applications toward floating-point solutions. Over the years, floating-point performance has more than doubled, while costs have dramatically dropped. Texas Instruments, for instance, will sample a DSP this year that boasts 1350 million floating-point operations per second. Furthermore, it will offer an appropriate mix of peripherals, memory, and interfaces to keep system cost low. Another major competitor advancing in this front is Analog Devices (ADI, www.analog.com). The company is touting a 1-GFLOPS DSP for its TigerSharc architecture with the right mix of peripherals, memory, buses, and interfaces to achieve lower system cost. This year, this next-generation DSP processor is slated to be fabricated in 0.13-µm CMOS. ADI's roadmap points toward 0.1-µm features in the near futurbe.
Whether embedding DSP cores in an ASIC solution or programming single-chip DSP processors, fully integrated development tools support them. Furthermore, they're refurbished continually to take advantage of the latest architectural enhancements and let DSP developers get started before the samples arrive.
Core developers are unleashing raw processing power and slashing power consumption by combining the advances in CMOS processes with architectural enhancements. While traditional suppliers have been fortifying their fixed-point DSP cores with more MAC units and datapaths with special-purpose instructions, a number of fabless design houses have created powerful synthesizable DSP cores with extreme parallelism on-board. Expected to give traditional DSPs tough competition, the new cores combine over 100 PEs in parallel configurations to let DSP developers map the connectivity and processing needs of an algorithm to the architecture.
Fixed-point DSPs have enabled cellular communications and continue to drive many more new wireless applications. So the need to get "more for less" is forcing suppliers to keep improving the DSP architecture. Merging very-long-instruction-word (VLIW) and single-instruction multidata (SIMD) techniques has maximized juice from a minimal die with several-fold improvement in power consumption. Dedicated coprocessors and optimized peripherals support this architecture to realize optimized solutions for specific market segments. On the packaging front, these devices will go from BGAs to chipscale packages in the near future.
See associated timeline.