Increased availability of dedicated and configurable analog functions to provide a "real world" connection to digital system logic will greatly reduce system complexity and component count.
More dedicated on-chip functions will help reduce overall design time. More CPU choices will be available, as will functions like phase-locked loops, DRAM controllers, and high-speed serial interfaces.
In addition to the reprogrammable aspects, designers will find ways to reuse logic, reducing the amount of silicon needed to provide a system solution. Thus, on a cycle-by-cycle basis, the FPGA can be reconfigured to perform different functions.
The use of deep-submicron processes will permit very high-speed operation, perhaps 400 to 600 MHz for logic functions and up to 5 GHz for high-speed serial I/O interfaces.
Greatly improved functional capture, synthesis, and timing analysis tools will considerably reduce the design cycle time by minimizing the number of spins necessary to complete a design.
Increased use of multilevel copper metallization to reduce interconnect delays and allow seven or more layers of interconnect will improve the gate utilization on FPGAs and reduce propagation delays, increasing overall performance.
Blocks of FPGA gates will become megacells for use in ASICs, letting designers complete chips faster. Designers can then perform final logic configuration after processing by loading the desired logic bit pattern into the FPGA memory.
Greater availability of well-defined blocks of "soft" intellectual property. Design reuse will become more important as the complexity of a function continues to increase.
Much denser FPGAs will be released this year. Gate counts will hit 3 million by 2003 and close to 5 million by 2005. Such high gate counts will allow FPGAs to offer true system-on-a-chip (SoC) solutions.
The use of lower operating voltages will ensure that active power doesn't overwhelm designs as densities move toward the multimillion-gate realm. Overall power consumption will be an important issue because FPGA suppliers can't predict the functions that designers will instantiate in logic.
See associated timeline.