EDA Alert: December 4, 2007

Two changes will occur in manufacturing test products in response to market pressures: embedded compression tools and logic built-in self test (LBIST) will converge; and manufacturing test tools will be integrated with yield and failure-analysis tools and looped back into design tools to improve yield for ICs at 65 nm and below.

A partnership between Tensilica Inc. and eASIC Corp. aims to lower the costs of developing custom embedded SoCs by enabling eASIC to provide free access to Tensilica's Diamond Standard microprocessor and DSP cores for its free mask charge, no-minimum-order ASICs. Through this partnership, embedded system designers can now develop Diamond processor-based SoCs for applications in any production volume.

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks' Simulink HDL Coder users gain a smooth path into synthesis. Mentor's Precision Synthesis tool now supports HDL generated by Simulink HDL Coder, enabling users to directly create optimized netlists for FPGAs.

Designers of high-speed and complex wireless SoCs and RFICs need a means of creating passive components. Cadence's Virtuoso Passive Component Designer represents a complete flow for the design, analysis, and modeling of inductors, transformers and transmission lines.

Shrinking process geometries and circuit complexity have conspired to create an explosion in data volumes for advanced IC manufacturing. Dealing with the oceans of data can result in longer development times. Most deeply affected are the mask-synthesis steps (RET and OPC) and mask-data preparation (MDP).

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