EDA Alert: November 13, 2007

Even as leakage overwhelms their power budgets, IC design teams are finding ways to plug the holes that are costing them dearly at sub-micron nodes...

Today, up to 80% of new ASIC and FPGA designs reuse RTL code from previous designs, and many design teams are embracing SystemVerilog, which was built with design reuse in mind. To support the ongoing adoption of SystemVerilog, Mentor Graphics has retooled its HDL Designer series of products to provide a platform for SystemVerilog design and verification...

In its 2008 release of the Advanced Design System (ADS) for high-frequency, high-speed circuit design, Agilent's tool developers have turned their attention to speed and productivity...

Many EDA applications, particularly simulation, require a great deal of computing horsepower to offset the long runtimes associated with complex designs. GiDEL's PROCStarIII family of FPGA-based accelerators could serve to break the computing logjam...

The Interoperable PCell Libraries (IPL) Initiative has issued an open invitation to semiconductor companies, foundries, integrated device manufacturers (IDMs), and EDA companies to join its three newest technical working groups...

• IBM and Intel revise the transistor
• The FCC decides to sell analog TV's 700-MHz spectrum
• 45-nm processors go into production
• The iPhone debuts and gets hacked
• AMD and Intel quad-core processors square off
• Other