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Embedded 32-Bit Cores Hit 1 GHz

Advanced pipeline designs and SIMD support push the limits of 32-bit microcontroller architectures.

Date Posted: October 25, 2007 12:00 AM
Author: William Wong

Head to head
The MIPS32 74K and Cortex-A9 are essentially the same in terms of performance and target audience. They're rated at 1.8 DMIPS/MHz and 2.0 DMIPS/MHz, respectively. Both can be configured with different size and complexity caches, and they can be surrounded with a range of standard peripherals. This silicon ecosystem often makes the difference when creating a system design.

Both cores utilize a TSMC 65-nm generic process. MIPS is the first company out of the chute with implementations in the gigahertz range. The Cortex-A9 will likely start out at about 500 MHz, climbing quickly to 1 GHz, given the demand for higher performance.

The two cores are close in size as well. The 74K core is about 1.7 mm2, while the Cortex-A9 is about 1.5 mm2. The difference is minor, and the final size of a chip will vary significantly based upon other factors such as cache size, peripherals, and the number and width of buses employed. Designers have a wide range of options with both architectures.

The companies take a similar third-party approach to software. They also include their own C/C++ tools. ARM has its RealView compiler suite, while the MIPS Software Toolkit combines open-source tools that have been optimized for the MIPS platforms.

ARM www.arm.com

MIPS www.mips.com

Arm Cortex-A9

Processor: 32 bits
Clock: 1 GHz
Multicore: up to four cores
Pipeline: eight-stage pipeline, out-of-order (OoO) instruction dispatch and completion, dispatch up to four instructions per clock cycle
MMU: TrustZone five-level security system
Instruction: Thumb-2, Jazelle RCT Java acceleration, ARM Neon Advanced SIMD support for accelerated media and signal-processing computation
Graphics: ARM Mali graphics processing unit
Floating point: IEEE-754-compliant

 

MIPS32 74K

Processor: 32 bits
Clock: 1.04 GHz
Pipeline: Superscalar dual-issue pipeline, out-of-order dispatch, 17-stage pipeline
MMU: dual-entry, dual-ported TLB shared, optional simple Fixed Mapping Translation (FMT) mechanism
Branch support: three 256-entry branch history tables, eight-entry return prediction stack
Instruction: four instruction fetches per cycle, CorExtend extensions, DSP, SIMD instructions
Floating point: IEEE-754-compliant, separate in-order dual-issue pipeline

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